Split from: ADC outputting 0,1023 (or 255)

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Hi @mikech,

 

I am trying to understand the functioning of the ADC on my UC3 device and having followed several posts, I got here.

 

The code is from a project in which the originator had the following setting for clocks:

OSC0 - 16MHz

PLL0 - 96Mhz

MainClock - 48MHz

PBA/PBB Clock -24MHz

CLK_ADC = PBA CLK = 24Mhz

 

static void setMainClock(void)
{
    //// Enable the external Osc0 of 16Mhz
    pm_enable_osc0_crystal(&AVR32_PM, FOSC0);
    
    pm_enable_clk0(&AVR32_PM, 0x00000003);
    
    ////Enable the PLL at 96MHz
    pm_pll_setup(&AVR32_PM, 0, 2, 0, 0, 16);
    
    //////PLL output VCO frequency at 48MHz
    //pm_pll_set_option(&AVR32_PM, 0, 0, 1, 0);
    pm_pll_set_option(&AVR32_PM, 0, 1, 1, 0);
    
    //////Enable PLL0
    pm_pll_enable(&AVR32_PM, 0);
    
    ///////Wait for PLL0 locked
    pm_wait_for_pll0_locked(&AVR32_PM) ;
    
    //////Set PBA and PBB clocks by 2 from main clock at 24 MHz
    pm_cksel(&AVR32_PM, 1, 0, 1, 0, 0, 0); //default
    
    /////Set PLL0 as main clock to 48MHz
    pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCSEL_PLL0); //default
}

 

AVR32_ADC.mr |= 0x4 << AVR32_ADC_MR_PRESCAL_OFFSET; // ~ 4.8 MHz

From the "AVR32_ADC.mr |= 0x4 << AVR32_ADC_MR_PRESCAL_OFFSET; // ~ 4.8 MHz" is this correctly 4.8MHz or 2.4MHz? My calculations says it is 2.4MHz but the comments indicate 4.8MHz. And I am now somehow confused.

 

Also, how do I set/change sampling frequency of an UC3's ADC. The originator claimed he was using a sampling frequency 250Hz, but I can not see where to set such frequency. Please guide me.

 

Last Edited: Fri. Jun 29, 2018 - 08:39 PM
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Working through the code ;
pm_pll_setup(&AVR32_PM, 0, 2, 0, 0, 16); gives a mul of 2 and a div of 0 to the PLL which multiplies OSC0 by 2*(2+1) = 6 which gives a PLL Vco of 96 MHz.
pm_pll_set_option(&AVR32_PM, 0, 1, 1, 0); divides PLL Vco by 2 which gives a potential system clock of 48MHz.
pm_cksel(&AVR32_PM, 1, 0, 1, 0, 0, 0); //default takes the main system clock and divides it by 2 to produce the PBA and PBB clocks of 24MHz.
The scaling is 2^(sel+1) and 'sel' is 0 for the PBA and PBB.
(The //default comment is incorrect because the default is for no division of the PBA/PBB/HSB clocks).
The ADC prescale is given as 4 which divides the PBA clock by (4+1)*2 = 10, hence the ADC clock is 2.4MHz and the // ~ 4.8 MHz comment is incorrect (or was correct before someone decided to divide the PBA clock).


As for the sampling frequency, that will depend on what is triggering the ADC conversions.
The datasheet says that the ADC can be triggered from a timer or an external input, but my version of the datasheet doesn't go into much detail about those triggers.
Personally, I would just configure a timer for your desired sample-rate and then trigger a conversion off that. (eg. via a timer-interrupt or via frequent checking of the compare-status flag in the timer SR)

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Thanks for the response again @mikech.

 

I did not realise you have replied till I came checking the site again (I usually do receive email alerts).

 

Your response has given me a good understanding of configuring the ADC. I was thinking the 2.4MHz was the sampling rate before, not realising there was need to be a timer-interrupt. I will get to fix this timer-interrupt and hopefully i will achieve my target sampling frequency of 250Hz. That I plan to do with: cpu_delay_us(4000, 3*BOARD_OSC0_HZ);

 

A side question is- is the ADC clock of 2.4Mhz sufficient? What guides the setting/configuration of this clock?

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In the Electrical Characteristics section of the datasheet there is a subsection which describes the ADC characteristics.
For the UC3Axxx the maximum ADC clock is 5 MHz for 10-bit conversions and 8 MHz for 8-bit conversions.
With a 5 MHz ADC clock the maximum throughput rate is 384 kSPS (which is the result from 3 ADC clocks for the sample-and-hold plus 10 for the conversion),
therefore with a 2.4 MHz ADC clock you should get approximately 2.4E6/13 = 184 kSPS throughput.