spi_m_sync_set_baudrate sets SPI clock divisor on SAM V71

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Hello,

I have an Atmel Start project on SAM V71. I put bit rates in spi_m_sync_set_baudrate and was not getting the frequencies I was expecting.

 

When I tried on the V71, the spi_m_sync_set_baudrate sets the clock divisor field SCBR in SPI_CSR0 (SPI clock phase select register). The SCBR field is only 8 bits. The function does not check if the argument is out of bounds. On the V71, the initialization code makes the fperipheral_clock run at 150 MHz. I tested multiple values on spi_m_sync_set_baudrate() with a logic analyzer and I get a frequency of 150MHz / divisor.

 

I used this code:

 

#include <atmel_start.h>

int main(void)
{
	/* Initializes MCU, drivers and middleware */
	atmel_start_init();
	
	static uint8_t example_SPI_0[2] = {0x40, 0x05};
	
	struct io_descriptor *io;
	spi_m_sync_get_io_descriptor(&SPI_0, &io);  
	spi_m_sync_set_baudrate(&SPI_0, 150);  /*Found it sets divisor, not bit rate. 150 MHz /150 = 1 MHz */

	spi_m_sync_enable(&SPI_0);
			
	/* Replace with your application code */
	while (1) {


			gpio_set_pin_level(ARDUINO_D9, false);
			delay_us(10);
			io_write(io, example_SPI_0, 2);
			gpio_set_pin_level(ARDUINO_D9, true);
			delay_us(10);
			
	}
}

 

inside atmel_start_pins.h

 

#define ARDUINO_D9 GPIO(GPIO_PORTC, 9)