I want to use the SPI in slave mode in my communication system. Chip is a 8515. I didn't find any information when the SPI interrupt flag (SPIF) is set in this case. Datasheet says that in master mode SPIF is set when SS is driven low...but is it the same when the slave mode is used?
Or can write the data into TX shift register and when the master sets SS low and starts clocking after the the bytes (TX and RX) are shifted the SPIF generates the interrupt?
thanks for your help, Daniel