As an experiment on an existing product I am trying to eliminate an obsolete FPGA, by implementing an SPI Slave on an ATmega128. I need to sample 5 push-button switches and place the samples in the SPDR register for the SPI Master to read asynchronously. I had hoped in vain that a value once written to SPDR, the SPI data register, would be repeated on successive transactions from the SPI Master.
From the datasheet I understand that I can update SPDR whenever PB0(SS*) is inactive(high). Problem is I can't just test for that condition and assume it will continue to be true long enough to update SPDR. The next suggestion is to update SDPR in the interrupt routine before reading the incoming data from the SPI Master.
What happens in either case is that with no mechanical action anywhere near the front panel buttons, the SPDR contains the string of 1's meaning that no buttons are being depressed. Occasionally of byte of zeros is returned which I interpret as a "failure to update" SPDR in a timely fashion. This apparent multiple button depression drives the SPI Master absolutely "BATS".
My question: "Is there a reliable way to return a constant value on an SPI Slave port in an ATmega128?"