AVR Freaks

I guess the next step is to put master and slave on different boards so both ISRs can run concurrently.

@clawson said:

outputs a byte does not decrement the count - so the count will be off by one won't it?

Yes, fixed that. 

@ki0bk said:

What happens if you switch roles, make SPI1 the master and SPI0 the slave (SPI0 has higher priority then SPI1)?

Every other slave byte makes it through. 

@kabasan said:

SCK starts from the point of writing the data.
You are setting DIV128.
64CPU clocks up to the SCK up edge is the output setup period. And the next 64CPU clocks to the SCK down edge is the slave sampling period. At the total of 128CPU clocks finishes 1SCK clock.

I understand now.

The fix was indeed to put master and slave on two different MCUs.  The proof is in the logic analyzer capture:

MASTER code:

#include <string.h>
#include <avr/cpufunc.h>
#include <avr/interrupt.h>
#include <avr/io.h>
#include <avr/pgmspace.h>
#include <util/delay.h>
#include "port.h"


// state flags
#define SPI_BUSY_bm	(1 << 0)
#define SPI_MASTER_bm	(1 << 1)
#define SPI_ONLINE_bm	(1 << 7)


// i/o pin bitmaps
#define SCK0_bm			PIN5_bm	/* PORT_B */
#define MISO0_bm		PIN4_bm	/* PORT_B */
#define MOSI0_bm		PIN3_bm	/* PORT_B */
#define SS0_bm			PIN2_bm	/* PORT_B */


// miscel
#define SPIF_bm		        (1 << SPIF)
#define SPI_SPR_DIV_128_gc	3
#define SPI_BUFFER_SIZE		16
#define SS_DELAY_us		5


typedef struct spi_status_struct
{
    volatile char* rx_buf;		//!< buffer to transfer to/from
    volatile char* tx_buf;		//!< buffer to transfer to/from
    volatile uint8_t count;		//!< number of bytes left to transfer
    volatile uint8_t flags;		//!< state flags
} spi_status_t;


spi_status_t spi0_status;


int main(void)
{

    char spi0_rx_buffer[SPI_BUFFER_SIZE];
    char spi0_tx_buffer[SPI_BUFFER_SIZE];

    // init master SPI
    PORT_B.PORT = SS0_bm;
    PORT_B.DDR = MOSI0_bm | SS0_bm | SCK0_bm;
    SPCR0 = (1 << SPE) | (1 << MSTR) | SPI_SPR_DIV_128_gc;

    _delay_ms(1);
	
    do 
    {
	cli();

	// clear Rx buffers
	memset(spi0_rx_buffer, 0, SPI_BUFFER_SIZE);

	// load Tx buffers
	strcpy_P(spi0_tx_buffer, PSTR("MASTER"));

	// init spi0 status
	spi0_status.rx_buf = spi0_rx_buffer;
	spi0_status.tx_buf = spi0_tx_buffer;
	spi0_status.count = strlen(spi0_tx_buffer) - 1;
	spi0_status.flags = SPI_ONLINE_bm;
	SPCR0 = (1 << SPE) | (1 << SPIE) | (1 << MSTR) | SPI_SPR_DIV_128_gc;
	
	sei();

	// select and pause
	PORT_B.PORT &= ~SS0_bm;
	_delay_us(SS_DELAY_us);

	// output first byte from master
	SPDR0 = *spi0_status.tx_buf++;

	while (spi0_status.flags & SPI_BUSY_bm);
				
	_delay_ms(25);

    } while (1);
	
    return 0;
}


ISR(SPI0_STC_vect)
{
    if (spi0_status.count)
    {
	// transfer next byte
	*spi0_status.rx_buf++ = SPDR0;
	SPDR0 = *spi0_status.tx_buf++;
	spi0_status.count--;
    }
    else
    {
	// disable SPIF interrupt and clear BUSY flag
	spi0_status.flags = SPI_ONLINE_bm;
	SPCR0 = (1 << SPE) | (1 << MSTR);

	// pause and deselect
	_delay_us(SS_DELAY_us);
	PORT_B.PORT |= SS0_bm;

    }

}

SLAVE code:

#include <string.h>
#include <avr/cpufunc.h>
#include <avr/interrupt.h>
#include <avr/io.h>
#include <avr/pgmspace.h>
#include <util/delay.h>
#include "port.h"


// state flags
#define SPI_BUSY_bm		(1 << 0)
#define SPI_MASTER_bm	(1 << 1)
#define SPI_ONLINE_bm	(1 << 7)


// i/o pin bitmaps
#define SCK0_bm			PIN5_bm	/* PORT_B */
#define MISO0_bm		PIN4_bm	/* PORT_B */
#define MOSI0_bm		PIN3_bm	/* PORT_B */
#define SS0_bm			PIN2_bm	/* PORT_B */


// miscel
#define SPIF_bm			    (1 << SPIF)
#define SPI_SPR_DIV_128_gc	3
#define SPI_BUFFER_SIZE		16
#define SS_DELAY_us		    5


typedef struct spi_status_struct
{
    volatile char* rx_buf;		//!< buffer to transfer to/from
    volatile char* tx_buf;		//!< buffer to transfer to/from
    volatile uint8_t count;		//!< number of bytes left to transfer
    volatile uint8_t flags;		//!< state flags
} spi_status_t;


spi_status_t spi0_status;


int main(void)
{

    char spi0_rx_buffer[SPI_BUFFER_SIZE];
    char spi0_tx_buffer[SPI_BUFFER_SIZE];

    // init slave SPI
    PORT_B.PORT = SS0_bm;
    PORT_B.DDR = MISO0_bm;
    SPCR0 = (1 << SPE);

    _delay_ms(1);
	
    do 
    {
	cli();

	// clear Rx buffers
	memset(spi0_rx_buffer, 0, SPI_BUFFER_SIZE);

	// load Tx buffers
	strcpy_P(spi0_tx_buffer, PSTR("SLAVE "));

	// init spi0 status
	spi0_status.rx_buf = spi0_rx_buffer;
	spi0_status.tx_buf = spi0_tx_buffer;
	spi0_status.count = strlen(spi0_tx_buffer) - 1;
	spi0_status.flags = SPI_ONLINE_bm;
	SPCR0 = (1 << SPE) | (1 << SPIE);
	
	sei();

	// output byte to be sent after slave is selected
	SPDR0 = *spi0_status.tx_buf++;

	while (spi0_status.flags & SPI_BUSY_bm);
				
	_delay_ms(20);

    } while (1);
	
    return 0;
}


ISR(SPI0_STC_vect)
{
    if (spi0_status.count && (!(PORT_B.PIN & SS0_bm)))
    {
	// transfer next byte
	*spi0_status.rx_buf++ = SPDR0;
	SPDR0 = *spi0_status.tx_buf++;
	spi0_status.count--;
    }
    else
    {
	// disable SPIF interrupt and clear BUSY flag
	spi0_status.flags = SPI_ONLINE_bm;
	SPCR0 = (1 << SPE);
    }
}