Split from :
The design of the spi block is the opposite; they try to shave the timing margins down to the minimum tolerable/usable margins (in order to allow for the fastest speeds). Why use the minimum possible safety margin, if you are not in a blazing hurry?
As I said in another thread discussing SPI - I think you are wrong. See my previous post: https://www.avrfreaks.net/comment/2811871#comment-2811871
If you still think that the AVR SPI block is badly designed and gives you bad timing margin - please provide an example. I cannot see how any external SPI device would NOT be compatible with at least some configuration (CPOL, CPHA, frequency) of the SPI block. After all SPI is nothing but clock and data at arbitrary rate.