i made a 4 layer custom PCB with 1 master MCU and 32 slave MCUs on. All the MCUs are Atmega3209. Basicaly the main MCU has 32 SS lines and activates each individual SLAVE, get data from it via SPI and after all data is gathered, the MASTER sends all the data via USART to PC. Basically all works like a charm, but then i wanted to speed SPI up, then the problems started. I set the SPI speed in register CTRLA, using prescalers. I tried all 4 options and at slow speeds (prescaler 128 and 64) things work perfect to ok, but at high speeds(prescaler 4 or 16) data gets garbled. I attached oscilloscope to MOSI, SCK and MISO lines and noticed that at higher speed the signals get garbled.
Now i ASSUME this is due to poor traces design, which causes stray capacitance/inductance at higher speeds, which makes problems when clock/data signal goes from high to low or vise versa. So now i am thinking what can i do on next PCB version to fix this? I planned on adding more layers and put SPI lines in between 2 ground planes and also increase spacing between them, to prevent this from happening to them. I also read some application notes on adding pullup/down resistors to help lines to switch faster. At the moment SPI traces are in same layer and next to other traces (5V/200mA power lines and UART lines).
In attachments are oscilloscope pictures of signals at different prescalers.