I'm using a CTC interrupt from a 16-bit timer. I'm wondering if its at all possible to prevent the clearing of the timer when the ISR is called?
Reason why I'm asking is because I'm also using the 16-bit timer for other tasks which require it to be continuous/free-flowing.
By definition the Clear Timer on Compare match means its probably not possible, but was hoping maybe there is some clever trick to possibly undo the clearing of the timer, or an alternative method.
You answered your own question - that's what CTC stands for - you need to use one of the other modes if you want it to count on to 0xFFFF and wrap.
If you're using CTC mode, the counter is supposed to clear on a match. But if you use normal mode, it should be possible to generate a compare match interrupt somewhere between 0 and 2^16, without the counter clearing before it rolls over. Or have I missed something here?
From the Mega48/88/168 datasheet (p. 116 in my copy):
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
Yea just looking at the data sheet, and it seems its possible. If the CTC interrupt is disabled, I could poll the Output Compare Flag (OCFnx) in normal mode, and hence high CPU usage from polling.
But do you need to poll the flag? As I understand it, the key is to use normal mode. In CTC mode the counter will clear when a match occurs, whether an interrupt is enabled or not. Correspondingly, in normal mode the counter should not clear before the maximum value (2^16-1) is reached, independant of which interrupts that are enabled. In other words, I think use can just switch to normal mode and still use a compare match interrupt.
Since overflow interrupt has its own interrupt vector, it should be possible to have both compare match as well as overflow interrupts enabled. Well, that's how I understand it. Should be fairly easy to test though.
There is no CTC interrupt (that I know of), so I assume you mean timer1 overflow interrupt. Take a look at the datasheet under TIFR1, the timer1 flags register. These flags determine when the interrupt fires, so when you want to figure out which interrupt will fire when, look at the flags register. For example, if you look at OCF1A, it says the flag will be set 1 cycle after TCNT1 = OCR1A. A match occurs, the flag is set. No match, no flag, no interrupt. That's it. (If you look at the 'Output Compare Unit, Block Diagram', you will see the OCF1x flags are set if a match occurs, and does not depend on which timer mode you are in).
So if you want the timer to count to 0xFFFF (normal mode), you can still set OCR1A,OCR1B to whatever value you want to also use those interrupts. IF you have the time, you can also keep moving those OCR1x values up in the irq. So if you want the compareA irq to fire every 20,000 counts in normal mode, just add 20,000 to the OCR1x register in the irq. The timer keeps going, new value loaded, compareA irq again in 20,000 counts.
The TOV1 and ICR1 flags depend on which mode you are in.
The timer is a beast, but if you look at the 'Waveform Generation Mode Bit Description' table, it can help make some sense of it. TOP column determines how high to count, the 'Update of OCR1X at' column is for pwm modes (when to update new OCR1x values), and the 'TOV1 Flag Set on' column determines when the TOV1 flag will be set. If you see 'Phase' in the description, that will tell you that the count will go up and down, not just up..
Great, it works! From what knutbr said, all I did was put it in normal mode (as opposed to CTC mode), and it worked. No more clearing of the timer. Thats saved a major headache. Now I have a 8-ch pwm servo driver and 8ch pwm reader from a r/c receiver, all running off one 16-bit timer, using minimal CPU time.
