Softcores on FPGA

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jayjay1974
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Posted by jayjay1974: Sat. Jun 25, 2011 - 06:27 PM
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[This thread split off from: https://www.avrfreaks.net/index.p... ]

Quote:
I do not see the purpose of overwriting the flash with the same content all over again

There's an option somewhere that only reloads the Flash when the object file has changed.

Quote:
n FPGA chip with 500k gates and a soft core of an AVR, nobody is going to play with OCD, as you can add literally any functionality, timers, counters, and trigger on just any event you can even imagine.. But this is still off topic.

I've actually been there, and you really need a debugger too with a softcore on an FPGA ;) Nice touch is that you can also load the FPGA (along with your own logic) with a logic analyser with inputs and triggers of your choice. The JTAG is used as the comms channel.

One problem with an FPGA is that you really want to limit the number of debug/burn cycles of the logic (not the software which can be uploaded apart from the logic configuration). A recomplication of the logic can easily take hours.

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Learning and Information, General Electronics
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Brutte
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Posted by Brutte: Sat. Jun 25, 2011 - 07:04 PM
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jayjay1974 wrote:
There's an option somewhere that only reloads the Flash when the object file has changed.

The file changes when you recompile. As I said - when I modify eeprom only, flash content stays the same(and vice versa). AVR Studio does not compare flash *.hex content, but the object file so IMHO this option will not prevent flash from being overwritten once again with the same pattern after new assemblation(as I am currently writing in asm). I wonder if on lower level the dongle does not check if the flash page which is to be overwritten can be skipped/written only, as nothing changed/can be anded .. Saving erase cycles...

jayjay1974 wrote:
with a logic analyzer with inputs and triggers of your choice.

That would be a really useful tool/environment. If you were bored with m164, you just pick m641 (if there is such AVR) from the library. With OCD I think comparing a register with some configurable value would be great on AVRs.. Just adding to my wishlist.

No RSTDISBL, no fun!

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jayjay1974
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Posted by jayjay1974: Sat. Jun 25, 2011 - 07:34 PM
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The typical softcore system allows you to choose a variant of CPU, like with or without instruction cache, data cache, single cycle multiplier, custom instructions you designed, etc.

Peripherals and memories are added to this. Choose from timers, UARTs, SPI modules, USB and whatever other logic you require. Including designs of your own with possibilities like busmastering etc.

E.g. it's fully customizable to your needs. You don't have to choose from a list of predetermined variants like you have to with real hardware.

Altera NIOS II

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Brutte
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Posted by Brutte: Sat. Jun 25, 2011 - 07:49 PM
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They have a PIC, but no AVRs!!

That is even more off-topic than it was when we were chatting about oscilloscopes. If you want, we can start a new thread about soft cores (in General Electronics)?

Could some moderator move the head of this thread to a more appropriate forum, please?

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Brutte
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Posted by Brutte: Mon. Jun 27, 2011 - 11:51 AM
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@jayjay1974
I wonder if anybody from AVRFreaks has a practical experience on FPGA + softcore, but not for production version (which has fast TTM and $$), but solely for development stage.
And although this is not an AVR forum (but General Electronics) and a 64-bit core implementation in FPGA is the right subject to discuss in here, I would rather if this thread was devoted to the smallest and available platforms (fixed point, ~8bit) used for development, and ported to the release chips finally.

No RSTDISBL, no fun!

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leon_heller
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Posted by leon_heller: Mon. Jun 27, 2011 - 01:22 PM
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AVR softcores are available:

http://opencores.org/project,avr_hp

Some others are also available there.

I've started creating a web page on how to get started with FPGAs quite cheaply:

http://www.leonheller.com/FPGA/F...

Leon Heller G1HSM

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jayjay1974
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Posted by jayjay1974: Mon. Jun 27, 2011 - 07:24 PM
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I once designed a machine controller with an Altera Cyclone 1C6 running a NIOSII and bit of extra logic to handle a SPI ADC with direct memory writing and synchronization to an external shaft encoder. Adding ICP-like functionality is like 10, 15 lines of VHDL; at any desired bit width(24 bits in this case). The ability to tailor interface peripherals to your exacts need is quite nice.

Years ago I tried to implement, almost gate for gate, the processor of Hewlett Packard's first scientific calculator, the HP-35. Logic and source code can be found in the patents, but I never got round making it actually fully work.

Other stuff I did with FPGAs included a JPEG IDCT processor, color space converters, LCD drivers etc.

If you have a grasp on how digital logic works, VHDL/Verilog is not that hard to understand and use, but it seems very hard for pure software people.

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fleemy
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Posted by fleemy: Mon. Jun 27, 2011 - 07:36 PM
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Isn't it so, that when you ‘implement’ a known microprocessor in a FPGA, that you need to pay for copyright, when using an existing(patented) microprocessor core(I thought I read that somewhere on the Altera site)?

Or can you just, say pick an existing 8-bit AVR core, any copy it on an FPGA(that would surprise me)?

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leon_heller
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Posted by leon_heller: Mon. Jun 27, 2011 - 08:55 PM
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ARM threatened to sue some students who created a synthesisable ARM core a few years ago and made it generally available - they had to remove it from their web site. I've got a copy of it somewhere. ARM now supplies something similar, at a price.

I don't think that Atmel is all that concerned about FPGA implementations.

Leon Heller G1HSM

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