Smiley NV article Dec 2010

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Nuts 'n Volts (when will they change that title?), 12/2010 issue, Smiley's #29 on pag. 62:

Fig 2 seems wrong: like the publisher used the wrong artwork - missing independent SS outputs from master?

On Fig 3: I've not seen daisy-chained serial data in SPI. But my experience is limited. What does the standard say that an SPI device whose SS is false must do re passing MOSI to MISO?

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stevech wrote:
Nuts 'n Volts (when will they change that title?), 12/2010 issue, Smiley's #29 on pag. 62:

Fig 2 seems wrong: like the publisher used the wrong artwork - missing independent SS outputs from master?

On Fig 3: I've not seen daisy-chained serial data in SPI. But my experience is limited. What does the standard say that an SPI device whose SS is false must do re passing MOSI to MISO?

It is wrong. I sent them the correct image but they messed up. I've appended a web reduction. BTW the 'standard' is anything but standard, its more evolved than standardized. And daisy-chained works, I've used it with a '595 to good effect.

So, Steve, you actually read that um... stuff?

Smiley

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Ah common Joe, we all read the stuff! Steve is the only one that understands it, that all! :-)

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Why change the title? I like it! Been getting it since the late 70's or early 80's. They once put an ad in the nuts and volts that if you sent in $5 you would get it for free for life. I did it and have been getting it free since then. :) They can call it whatever they want too! As long as I keep getting it free.

Seeing smiley in there was cool.

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stevech wrote:

On Fig 3: I've not seen daisy-chained serial data in SPI. But my experience is limited. What does the standard say that an SPI device whose SS is false must do re passing MOSI to MISO?

the SPI "spec" only defines the electrical connections and the singnalling. Not any underlying protocol/framing. There is no such thing as a false SS, or at least no way to determine this. If a device has its SS line (CS on most devices) the device will receive whatever is presented on the SI pin, and possibly, depending on function, return something on the SO pin. If the device is not selected, both SI & SO are inactive. How a device reacts to invalid data that it is presented is up to the device, but this usually will result in some form of malfunction of your system.

Some devices operate in a shift through manner. In this case if you were to clock more bits than the device expects to receive, it starts presenting the oldest bits out on its SO pin. This allows additional devices to be daisy-chained in the system and to receive data. Each device only retains the last n bits it receives. [where n is the number of bits it expects] If there are no more devices in the chain the additional bits are lost [or possibly received back by the master if a closed loop] In the daisy-chan configuration, all the devices in the chain share the same SS from the master. In turn the master must shift enough data to properly load the input buffers of all the devices in the chain.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

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Quote:
If a device has its SS line (CS on most devices) the device will receive whatever is presented on the SI pin, and possibly, depending on function, return something on the SO pin. If the device is not selected, both SI & SO are inactive. How a device reacts to invalid data that it is presented is up to the device, but this usually will result in some form of malfunction of your system.
that's what I wondered- in the daisy-chained arrangement. Not sure every vendor/part will repeat the data out.
Moreover, I don't get the idea of how you address/select a single chip with the daisy-chain scheme. Maybe the 'standard' has chip addresses but I don't recall ever seeing it or using it - I always see multiple SS lines.

I'm interested as I'm adding an SD card to a design that already uses SPI to talk to a WizNet 812MJ ethernet interface. I think I'll not try the daisy-chain scheme.

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In the olden days, we'd write articles for the trade journals like EE times, etc. Non-refereed articles so they will be published before the end of the world, unlike IEEE. And get a few bucks. Looks good on the resume. But not so much, to cite articles in Nuts 'n Volts. Circuit Cellar is not so hot either as a title. Years ago I wrote for early microprocessor hobby magazines with fancy titles and the employer didn't know it was really a hobby pub.

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Aha. I see. So even pointy haired bosses can read Nuts and Volts and figure out it might not be scholarly? :)

It started out as a pennysaver ad rag type of thing with ads for stuff for sale only. Then there were some tiny articles. Then the paper got all shiny...

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stevech wrote:

Moreover, I don't get the idea of how you address/select a single chip with the daisy-chain scheme.

You don't. The chain is addressed like a single chip. There is no way to address a single chip within the chain. It is simply one giant shift-register.

Daisy chaining is not a universal option, only some devices can be operated in this manner. The only universal option is using individual chip selects.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

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You write out and read in as many bits as in the chain. If you've got 8 '595, then you send out 64 bits. I discussed this in some detail for a software SPI in the previous month's article, where I used two '595 to run 16 LEDs for a Chaser Light project.

And no you wouldn't daisy chain an SD card. For the ones I've seen you send out 8-bit while receiving 8-bits.

Smiley

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Daisy-chaining like-kind and certain types of chips with SPI. I get it now.

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Please note the difference between SPI devices and serial-in shiftregisters (and similars).

It's not possible to daisy-chain ANY SPI device. An SPI device that relays data to (or in any way activate) MISO when it's CS line is inactive, would be useless in a regular SPI bus system.

For shiftregisters that have a LOAD pin instead, this is a completely different story, and daisy-chaining works fine, which is not surprising as the devices were designed for this.

/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.

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smiley, the DataFlashTest project is not inside of the ZIP file for Workshop29

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Thank you, sir. I see that you have included the DataFlashTest project into the ZIP file for Workshop 30, so readers can now have access to it from either place.

From the December article, "...then we write the first array to buffer 1, read buffer 1 into the second array, and show them again...". This sentence was the source of my confusion, because it omits the critical part of the function, which is to write the buffer into the flash page, then to read the flash page back into the buffer, and then to read the buffer into the array.

Now that I understand it from seeing the source code, I may get out in front of you before I see the next Workshop, although I know it is now imminent. I'll just improve my stuff with yours when I see it.

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I just reread that section and it was a bit cryptic even to me and I wrote it! I was testing reads and writes to the SRAM buffers on the DataFlash chip, but not actually telling it to write those buffers to the Flash. Sorry for the confusion.

Smiley