Simulator UsART UDRE bit bug?

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hi,

 

I have a simple ISR that triggers on Timer1 CompareA match:

 

	  while (! (UCSRA & (1<<UDRE)) ); //wait for empty transmit buffer
	  UDR = 0xF8; //Put data into buffer, write.

and the disassembly:

 

   114: ISR(TIMER1_COMPA_vect){
00000024 1f.92                PUSH R1		Push register on stack 
00000025 0f.92                PUSH R0		Push register on stack 
00000026 0f.b6                IN R0,0x3F		In from I/O location 
00000027 0f.92                PUSH R0		Push register on stack 
00000028 11.24                CLR R1		Clear Register 
00000029 8f.93                PUSH R24		Push register on stack 
    96: 	  while (! (UCSRA & (1<<UDRE)) ); //wait for empty transmit buffer
0000002A 5d.9b                SBIS 0x0B,5		Skip if bit in I/O register set 
0000002B fe.cf                RJMP PC-0x0001		Relative jump 
    97: 	  UDR = 0xF8; //Put data into buffer, write.
0000002C 88.ef                LDI R24,0xF8		Load immediate 
0000002D 8c.b9                OUT 0x0C,R24		Out to I/O location 
   116: }
0000002E 8f.91                POP R24		Pop register from stack 
0000002F 0f.90                POP R0		Pop register from stack 
00000030 0f.be                OUT 0x3F,R0		Out to I/O location 
00000031 0f.90                POP R0		Pop register from stack 
00000032 1f.90                POP R1		Pop register from stack 
00000033 18.95                RETI 		Interrupt return 

When the ISR executes for the first time during debugging in step mode (i.e. I'm using step into) the UDRE bit in the I/O view is not cleared after 

0000002D 8c.b9                OUT 0x0C,R24		Out to I/O location 

, the second ISR execution an onwards it works as it supposed to, i.e. the UDRE bit clears and only sets after the appropriate amount of mS/Clock cycles (depending on the baud rate setting). Is this a bug or perhaps I'm missing something?