Over several years of work with 8-bit AVRs, I've never had problems with signal integrity, even when running signals up to 3Mhz over 50cm long ribbon cable. Over the past couple weeks, I've been building a SWD probe using a CH552 (8051) MCU, and have encountered repeated communications problems. I did have a flaky solder joint on one of my connection, but after fixing it the communications problems persisted. After noticing a lot of ringing, I tried adding 68-Ohm series resistors on SWCLK and SWDIO, which eliminated the problems. I'm somewhat limited by the 1Gsps resolution of my scope, but I can tell the CH552 has much faster rise times, around 1-2ns, than the AVR parts I'm used to using that are around 3-4ns. I measured the output impedance of the CH552 IO at about 80Ohms. The AVRs I've used have around 25Ohm output impedance, which implies much bigger FETs on the output totem pole, and therefore higher gate capacitance and slower switching times. The CH552, like 8-bit AVRs, has no slew rate control.
I suspect the 28AWG 0.1" dupont jumper wire ribbon cable I'm using has an impedance around 150 Ohms, so the 68Ohm series resistors should make for good impedance matching. I still see some overshoot, which after reading up on transmission lines I understand is to be expected given the high impedance at the receiver. Since the transmit side is impedance matched, I think the reflection from the receive side should be almost fully attenuated, and avoid the negative reflection back to the receiver that was likely causing excessive ringing before I added the series resistors.
Now that I've gone down this deep rabbit hole of velocity factors, inductive coupling, and capacitive coupling, I'm interested in understanding it as best I can. I've seen other schematics where series resistors are used for impedance matching, and I've also seen schematics showing small caps (~100pF) which I assume are there to reduce both noise and slow rise/fall times. My guess is the total capacitance of the SWCLK and SWDIO lines is around 30-40pF. I'm wondering if it is a good idea to add capacitance as well. If I understand the physics correctly, using low-impedance MLCC capacitors alone (without series resistors) would reduce the rise times but would increase the source impedance mismatch and therefore possibly increase the negative reflections back to the receiver.
When researching this subject I found a few resources like impedance calculators for PCB traces, but never saw anything relevant dealing with signals over cable assemblies. Does anyone have any suggested reading material? While some old papers discussing SCSI bus terminations and ATA-133 are interesting reading, it's not that helpful for a SWD probe connecting to a target board with hiZ inputs. I've read through the ARM SWD (ADI) spec, and there's surprisingly little consideration given to the physical layer. It calls for a 100k pullup on SWDIO, but makes no mention at all of any signal timing such as minimum SWCLK high and low periods, rise/fall times, etc.