SDRAM problem: about 3% error rate

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t0mmy
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Posted by t0mmy: Sun. Jul 19, 2009 - 09:52 AM
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Hello,

I have designed a custom board with the uc3a0512 and external SDRAM. It is the MT48LC4M16A2P-7E (8MByte), a small version from the chip soldered on the EVK1100.

I got it running without any problems, but then I did a test and discovered, that sometimes it reads (or writes) not the correct values.

The EVK1100 SDRAM example also says "SDRAM tested: 1567941 corrupted word(s)"

Almost the same from 12Mhz to 66MHz CPU clock.

I tried using the timings from the MT48LC16M16A2TG7E-driver, changing the row- and col-bit numbers and also using the timings from the datasheet - always the same.

This is my first experience with SDRAM and I have no idea whats wrong here. I hope the layout is not that worse...

Maybe you have some ideas for me? I'm playing around with that for three days now.
Thanks!

Attachment(s): 

Plain text icon that's how I connected the sdram to the avr32 (should be same as EVK1100)

Student at the University of Applied Sciences Ulm, Germany

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Tools, Evaluation and Development Kits (AVR-related)
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Heihopp
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Posted by Heihopp: Sun. Jul 19, 2009 - 04:01 PM
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What do the second pad on the capacitors route to? I cannot see a connection there, it should be a ground plane.

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t0mmy
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Posted by t0mmy: Sun. Jul 19, 2009 - 05:35 PM
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Thanks for your response. Yes this pad is actually connected to the groundplane. The groundplane is not visible in this picture for a better view to the bottom layer.

But the really much more important new is: I just found the cause for my problem. I had some pins on the avr with bad soldering. Should have checked that before...

Shame one me... :oops:

Student at the University of Applied Sciences Ulm, Germany

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Heihopp
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Posted by Heihopp: Sun. Jul 19, 2009 - 05:42 PM
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Good! Please let us know how it works when you have fixed the problem. I am curently working on a similar board, but havent ordered it yet.

Btw, are the cap #2 pads connected to the other layer inside the pad, or did you add the traces later on after the screeshot?

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t0mmy
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Posted by t0mmy: Sun. Jul 19, 2009 - 06:26 PM
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Heihopp wrote:
Good! Please let us know how it works when you have fixed the problem. I am curently working on a similar board, but havent ordered it yet.

Btw, are the cap #2 pads connected to the other layer inside the pad, or did you add the traces later on after the screeshot?

The Layout is made with eagle. There it is possible to not show the (ground-)polygonareas. Heres a picture with the groundplanes.

The SDRAM-Example runs fine with 0 Errors. Next I am going to put the HEAP in the SDRAM, i hope that will work a little bit faster.

Attachment(s): 

Image icon layout.gif

Student at the University of Applied Sciences Ulm, Germany

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