SDRAM with cache

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Hello everybody. I have a SAME70-XPLAINED evaluation board . I want to use SDRAM.

In the standard flash file.ld, I added a section of sdram.

 

/* Memory Spaces Definitions */
MEMORY
{
  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00200000
  ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000
  sdram (rwxa) : ORIGIN = 0x70000000, LENGTH = 0x00200000
}

//............

/* Section Definitions */
SECTIONS
{
//............
 .data_sdram ORIGIN(sdram) :
 {
  . = ALIGN(4);
  PROVIDE(_data_sdram = .);
  *(.data_sdram)
  . = ALIGN(8);
  PROVIDE(_edata_sdram = .);
 } >sdram
}

Wrote a test program:

 

#define array_size 32
__attribute__((__section__(".data_sdram"))) int16_t array[array_size];

//.............

int main(void)
{
 /* Initialize the system */
 sysclk_init();
 board_init();
 sleepmgr_init();

 /* Configure the console uart */
 configure_console();

 /* Enable SDRAMC peripheral clock */
 pmc_enable_periph_clk(ID_SDRAMC);

 /* Complete SDRAM configuration */
 sdramc_init((sdramc_memory_dev_t *)&SDRAM_ISSI_IS42S16100E,
   sysclk_get_cpu_hz());
 sdram_enable_unaligned_support();

 /* Test external SDRAM access */
 puts("Test external SDRAM access. \r");
 
 SCB_CleanInvalidateDCache();

 for(int16_t i=0;i<array_size;i++)
 {
  array[i]=i;
 }

 for(int16_t i=0;i<array_size;i++)
 {
  if(array[i]==i)
   {
    puts("SDRAM access is ok.\n\r");
   }
  else
   {
     puts("SDRAM access is failed.\r");
   }
 }
  

 for (;;) {
  sleepmgr_enter_sleep();
 }
}

As a result, all elements of the array were read as zero.

 

Without using the cache, everything works. What should I do to use SDRAM with the cache?