SAML21 Freezes in system_gclk_chan_enable() Function.

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HI,

I'm working  USB CDC communication on SAML21. Here the issue i'm facing is system_gclk_chan_enable() is freezing on the while loop. The clock synchronization is not happening

void system_gclk_chan_enable(
		const uint8_t channel)
{
	system_interrupt_enter_critical_section();

	/* Enable the peripheral channel */
	GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;

	while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
		/* Wait for clock synchronization */
	}

	system_interrupt_leave_critical_section();
}

Here in the while loop the code is hanging. I'm not clear why this is happening. Below i'm attaching the conf_clocks.h file. i'm stuck with this issue any help will be appreciated. 

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There is no 48 MHz config in the conf_clocks.h so will not work for USB. There are example projects for USB for SAML21 XPlained Pro.

/Lars

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Hi Lajon,

 

  I made the changes you suggested. I'm working on customised board. If i run the code for USB CDC on my board with the changes in clock.c &  conf_clocks.h. It will stuck system_clock_source_is_ready() in CONF_CLOCK_OSC32K_ENABLE == true.  I'm attaching the image(image1) below where  the code stuck. If i disable XOSC32K and   it will stuck on while loop below 

while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
		/* Wait for clock synchronization */
	}

 

I'm attaching the new  clock.c &  conf_clocks.h files below . 

 

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Do you actually have a 32768 Hz crystal mounted on your custom board? 

It's not impossible without but it looks like all SAML21 XPlained Pro examples make use of this. You can (probably) look at the SAMD21 examples for how to do it without a crystal (SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY).

/Lars

 

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Hi  Lajon ,

    

    Thank you for your support. If i run in  SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY  mode by disabling  XOSC32K  the clock syhnchronization is happening and it is stucking in

	uint32_t cpu_freq = system_cpu_clock_get_hz();
	if (cpu_freq <= 12000000) {
		system_switch_performance_level(SYSTEM_PERFORMANCE_LEVEL_0);
	}

.

 

  I read the data sheet i'm not able to understand how the clock works on usb. Here which clock act as the main clock?

  What is the difference between SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY & normal mode?.

 

Here is the code flow for SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY.

 

 void system_clock_init(void)-->_system_clock_source_osc16m_freq_sel();(/* OSC16M */)-->DFLL Config (Open and Closed Loop)(CONF_CLOCK_DFLL_ENABLE == true)-->

(/* GCLK */CONF_CLOCK_CONFIGURE_GCLK == true-->/* DFLL Enable (Open and Closed Loop) */(CONF_CLOCK_DFLL_ENABLE == true)-->/* CPU and BUS clocks */-->

(/* GCLK 0 */)CONF_CLOCK_CONFIGURE_GCLK == true.

 

ISSUE:

   

     I'm attaching the  .h file below .

 where i'm facing issue is  at the point with the configuration below the code is stopping.

uint32_t system_gclk_gen_get_hz(
		const uint8_t generator)
{
	while (system_gclk_is_syncing(generator)) {
		/* Wait for synchronization */	};
	system_interrupt_enter_critical_section();

	/* Get the frequency of the source connected to the GCLK generator */
	uint32_t gen_input_hz = system_clock_source_get_hz(  //stuck here
			(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
	uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
	uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
	system_interrupt_leave_critical_section();
	/* Check if the generator is using fractional or binary division */
	if (!divsel && divider > 1) {
		gen_input_hz /= divider;
	} else if (divsel) {
		gen_input_hz >>= (divider+1);
	}
	return gen_input_hz;
}

   

    

 

I'm attaching new conf_clock.h file below please check my configurations and how it will work.

Here i'm not clear about what each clock does . It will be helpful for me if you give me some inputs about the clocks in l21 and it significance & Difference between normal mode and recovery.

 

Thanks

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Last Edited: Fri. Mar 1, 2019 - 12:37 PM