SAME70 SPI with XDMAC in Linked list not working

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Hello All,

 

I have used SAME70 Explained Board SPI with XDMAC example , it worked.

 

I tried to modify the example by extending both Transmit and Receive with Linked list.

 

my XDMAC configuration is below , g_size is kept to 6 , the SPI is transmitting only first 6 bytes , next 6 bytes transmission is not happening .

 

uint32_t xdmaint;

    /* Initialize and enable DMA controller */
    pmc_enable_periph_clk(ID_XDMAC);

    xdmaint = (XDMAC_CIE_BIE |
    XDMAC_CIE_LIE   |
    XDMAC_CIE_DIE   |
    XDMAC_CIE_FIE   |
    XDMAC_CIE_RBIE  |
    XDMAC_CIE_WBIE  |
    XDMAC_CIE_ROIE);

    /* Initialize channel config for transmitter */
    xdmac_tx_cfg.mbr_ubc = g_size;

    xdmac_tx_cfg.mbr_sa = (uint32_t)tx_buffer;
    xdmac_tx_cfg.mbr_da = (uint32_t)&(pspi->SPI_TDR);
    xdmac_tx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
    XDMAC_CC_MBSIZE_SINGLE |
    XDMAC_CC_DSYNC_MEM2PER |
    XDMAC_CC_CSIZE_CHK_1 |
    XDMAC_CC_DWIDTH_BYTE |
    XDMAC_CC_SIF_AHB_IF0 |
    XDMAC_CC_DIF_AHB_IF1 |
    XDMAC_CC_SAM_INCREMENTED_AM |
    XDMAC_CC_DAM_FIXED_AM |
    XDMAC_CC_PERID(SPI0_XDMAC_TX_CH_NUM);

    xdmac_tx_cfg.mbr_bc = 0; //0
    xdmac_tx_cfg.mbr_ds =  0;
    xdmac_tx_cfg.mbr_sus = 0;
    xdmac_tx_cfg.mbr_dus = 0;

    xdmac_configure_transfer(XDMAC, XDMAC_TX_CH, &xdmac_tx_cfg);

    //xdmac_channel_set_descriptor_control(XDMAC, XDMAC_TX_CH, 0);
    
    lld_0[0].mbr_nda = 0;
    lld_0[0].mbr_ubc = XDMAC_UBC_NDE_FETCH_DIS | XDMAC_UBC_UBLEN(g_size);
    lld_0[0].mbr_sa = (uint32_t)&tx_buffer[6];
    lld_0[0].mbr_da = (uint32_t)&(pspi->SPI_TDR);
    lld_0[0].mbr_bc = 0;
    lld_0[0].mbr_ds = 0;
    lld_0[0].mbr_sus = 0;
    lld_0[0].mbr_dus = 0;
    lld_0[0].mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
    XDMAC_CC_MBSIZE_SINGLE |
    XDMAC_CC_DSYNC_MEM2PER |
    XDMAC_CC_CSIZE_CHK_1 |
    XDMAC_CC_DWIDTH_BYTE |
    XDMAC_CC_SIF_AHB_IF0 |
    XDMAC_CC_DIF_AHB_IF1 |
    XDMAC_CC_SAM_INCREMENTED_AM |
    XDMAC_CC_DAM_FIXED_AM |
    XDMAC_CC_PERID(SPI0_XDMAC_TX_CH_NUM);
    
    xdmac_channel_set_descriptor_control(XDMAC, XDMAC_TX_CH,
        XDMAC_CNDC_NDVIEW_NDV3    |
        XDMAC_CNDC_NDE_DSCR_FETCH_EN |
        XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |
        XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED);
    
    xdmac_channel_set_descriptor_addr(XDMAC, XDMAC_TX_CH, (uint32_t)(&lld_0[0]), 0);

    
//    xdmac_channel_enable_interrupt(XDMAC, XDMAC_TX_CH, xdmaint);
    xdmac_channel_enable(XDMAC, XDMAC_TX_CH);
//    xdmac_enable_interrupt(XDMAC, XDMAC_TX_CH);

    /* Initialize channel config for receiver */
    xdmac_rx_cfg.mbr_ubc = g_size;

    xdmac_rx_cfg.mbr_da = (uint32_t)rx_buffer;

    xdmac_rx_cfg.mbr_sa = (uint32_t)&pspi->SPI_RDR;
    xdmac_rx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
    XDMAC_CC_MBSIZE_SINGLE |
    XDMAC_CC_DSYNC_PER2MEM |
    XDMAC_CC_CSIZE_CHK_1 |
    XDMAC_CC_DWIDTH_BYTE|
    XDMAC_CC_SIF_AHB_IF1 |
    XDMAC_CC_DIF_AHB_IF0 |
    XDMAC_CC_SAM_FIXED_AM |
    XDMAC_CC_DAM_INCREMENTED_AM |
    XDMAC_CC_PERID(SPI0_XDMAC_RX_CH_NUM);

    xdmac_rx_cfg.mbr_bc = 0; //0
    xdmac_tx_cfg.mbr_ds =  0;
    xdmac_rx_cfg.mbr_sus = 0;
    xdmac_rx_cfg.mbr_dus =0;

    xdmac_configure_transfer(XDMAC, XDMAC_RX_CH, &xdmac_rx_cfg);

//    xdmac_channel_set_descriptor_control(XDMAC, XDMAC_RX_CH, 0);

    lld_1[0].mbr_nda = 0;
    lld_1[0].mbr_ubc = XDMAC_UBC_NDE_FETCH_DIS | XDMAC_UBC_UBLEN(g_size);
    lld_1[0].mbr_sa = (uint32_t)&pspi->SPI_RDR;
    lld_1[0].mbr_da = (uint32_t)&rx_buffer[6];
    lld_1[0].mbr_bc = 0;
    lld_1[0].mbr_ds = 0;
    lld_1[0].mbr_sus = 0;
    lld_1[0].mbr_dus = 0;
    lld_1[0].mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
    XDMAC_CC_MBSIZE_SINGLE |
    XDMAC_CC_DSYNC_PER2MEM |
    XDMAC_CC_CSIZE_CHK_1 |
    XDMAC_CC_DWIDTH_BYTE|
    XDMAC_CC_SIF_AHB_IF1 |
    XDMAC_CC_DIF_AHB_IF0 |
    XDMAC_CC_SAM_FIXED_AM |
    XDMAC_CC_DAM_INCREMENTED_AM |
    XDMAC_CC_PERID(SPI0_XDMAC_RX_CH_NUM);
    
    xdmac_channel_set_descriptor_control(XDMAC, XDMAC_RX_CH,
        XDMAC_CNDC_NDVIEW_NDV3    |
        XDMAC_CNDC_NDE_DSCR_FETCH_EN |
        XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |
        XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED);
    
    xdmac_channel_set_descriptor_addr(XDMAC, XDMAC_RX_CH, (uint32_t)(&lld_1[0]), 0);
//    xdmac_channel_enable_interrupt(XDMAC, XDMAC_RX_CH, xdmaint);
    xdmac_channel_enable(XDMAC, XDMAC_RX_CH);
//    xdmac_enable_interrupt(XDMAC, XDMAC_RX_CH);
        
    /*Enable XDMAC interrupt */
//    NVIC_ClearPendingIRQ(XDMAC_IRQn);
//    NVIC_SetPriority( XDMAC_IRQn ,1);
//    NVIC_EnableIRQ(XDMAC_IRQn);