SAME70 SDRAMC clock input

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Hello,
We have a custom board based on SAME70-XPlained, set at 300MHz, with IS42S16100H SDRAM chip. I cannot find in the MCU datasheet any information about which clock is driving SDRAMC peripheral, is it using the MAINCK or PLLA clock or the 150MHz master clock? This is our board clock setup:
12MHz crystal oscillator
PLLA Multiplier=24 PLLA clock=300MHz
Master clock: PLLA_CLK[X]
  masterClkPrescaler=1, Master clock=150MHz

The ASF and the datasheet mentions SDRAM timings values for 100MHz, but we noticed the heap is corrupted and processor goes into MemFault handler after a few seconds. The code runs fine from internal RAM so I don't think there are any leaks. This is the linker change in same70_flash.ld:
    .heap (NOLOAD):
    {
        . = ALIGN(8);
         _sheap = .;
        . = . + HEAP_SIZE;
        . = ALIGN(8);
        _eheap = .;
    } > sdram

Also, the SDRAM chip on the evaluation board, IS42S16100E, specifies 3 frequencies, 143, 166, 200MHz, can it work at 150MHz? We run some memory+address tests and they seem to pass so I think hardware and project configuration is fine but when firmware is used with malloc it crashes.

Thank you in advance, 
David.