SAME70 problem with HSMCI on 12.5Mhz+ on SDIO bus

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Our project is based on ASF3.51 and "same70 xplained" board.

We interface with BCM43455 Wifi module.

The test project is simple, all non related modules and peripherals are switched off. Only SDIO is active.

We communicate over SDIO bus to BCM43455 (AP6255 module fully works on our Android board), no other devices on this bus are present.

All works properly for the SDIO clock speed up to 12.5Mhz but after ramping up to 50Mhz we got periodic errors in data, the closer we are to 50Mhz the more errors we encounter. Rare errors at 25MHz.

Fail happen when we read the data via DMA in block mode (cmd53). There is 64 byte block size and 24 blocks resulting in 1536 byte packet size.

When error appears, we see that HSMCI stops receiving data for some reason. It always happens after 1408 bytes.

We see that HSMCI stops generating the master clock, the last 8 bytes sit in FIFO, DMA does not get the full block (64 bytes) and cannot generate XDMAC_CIS_BIS (end of block) interrupt.

SDIO mode used is: 4bit, 50Mhz, Voltage: 3.3V

When error happens the following is set:

HSMCI->HSMCI_SR:

    HSMCI_SR_XFRDONE == 1

    HSMCI_SR_FIFOEMPTY == 0

    HSMCI_SR_RXRDY == 1

 

Anyone ever had similar issues ? Are we doomed to use 50MHz with HSMCI ?

Filed the support ticket on Microchip support, no reply yet.

Any hints or directions are welcome !