AVR Freaks

I know this is an older post, but I wanted to add my feedback.  The OP is correct.  Atmel Start does not handle the clock divider going into either of the DPLLs properly.  Following is Figure 28-2 from the SAM-D5xE5x reference:

The clock divider (DPLLCTRLB.DIV) definitely occurs before the input to the DPLL.  This should allow either of the XOSCs to directly input into the DPLL without requiring use of an extra GCLK.  To verify this, I used the following code on my SAME54 Xplained board:

	// Run with a 12MHz external crystal on XOSC1
	OSCCTRL->XOSCCTRL[1].bit.ENALC      = 1;
	OSCCTRL->XOSCCTRL[1].bit.IMULT      = 4;
	OSCCTRL->XOSCCTRL[1].bit.IPTAT      = 3;
	OSCCTRL->XOSCCTRL[1].bit.ONDEMAND   = 0;
	OSCCTRL->XOSCCTRL[1].bit.XTALEN     = 1;
	OSCCTRL->XOSCCTRL[1].bit.ENABLE     = 1;
	// Wait for OSC to be ready
	while (0 == OSCCTRL->STATUS.bit.XOSCRDY1);

	// Set up DPLL0 to output 120MHz using XOSC1 output divided by 12 - max input to the PLL is 3.2MHz
	OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC  = 0;
	OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR      = 119;
	OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV      = 5; // 2 * (DIV + 1)
	OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK   = 3; // use XOSC1 clock reference
	OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
	OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE   = 1; // enable the PLL
	// Wait for PLL to be locked and ready
	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);

	// Connect DPLL0 to clock generator 0 (120MHz) - frequency used by CPU, AHB, APBA, APBB
	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
        while (1 == GCLK->SYNCBUSY.bit.GENCTRL0);
	

I can confirm that this works perfectly on my board at 120MHz.