SAME54, DMA response change during clock frequency change.

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Hi,

 

I am working on a project which supposed to sample an external ADC at regular intervals (at 16kHz).

 

The ADC conversion is triggered by Timer. This timer also generates an event to trigger a DMA based SPI transmission (two bytes each time).

An interrupt is triggered after several triggers to process the gathered data.

 

The processor goes into the standby mode between processing received data, and only SPI and the DMA is working at this time.

To save as much energy as possible, I decided to throttle the MCLK (which is also used to drive the DMA) during the sleep mode.

 

The problem is, that throttling the DMA clock is also altering DMA's response time.  This is most visible during the clock speed change event.

It causes the SPI packets not being sent in phase with the ADC trigger signal (acting also as the CS) during the clock speed change, and some of the SPI packets are lost.

 

Attached is a screenshot with signals:

  • D0-D2    SPI
  • D3 Trigger (from Timer), used also as a SPI CS signal
  • D4 Indicates When MCU is awake in with fast CLK.

 

 

 

Question:

Is there any way to force or tweak the DMA to let's say delay its response to an event in certain circumstances (i.e. switching it's CLK to a different frequency) ?

 

Last Edited: Fri. Oct 16, 2020 - 10:31 AM
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Gostek wrote:

Question:

Is there any way to force or tweak the DMA to let's say delay its response to an event in certain circumstances (i.e. switching it's CLK to a different frequency) ?

 

You could configure another GCLK with the same parameters as GCLK#0, and use that to clock the DMA controller. Ensure the selected GCLK's GENCTRLn.RUNSTDBY bit is set. Throttling GCLK#0 / MCLK will then have no impact on the DMA clock.

 

Steve

Maverick Embedded Technologies Ltd. Home of Maven and wAVR.

Maven: WiFi ARM Cortex-M Debugger/Programmer

wAVR: WiFi AVR ISP/PDI/uPDI Programmer

https://www.maverick-embedded.co...

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That would work, but how can I set a separate GCLK for DMA ?

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Ah, sorry; my mistake. The DMA controller is clocked from MCLK.

 

In that case, do you have the RUNSTDBY bit set for GCLK#0?

 

Steve

Maverick Embedded Technologies Ltd. Home of Maven and wAVR.

Maven: WiFi ARM Cortex-M Debugger/Programmer

wAVR: WiFi AVR ISP/PDI/uPDI Programmer

https://www.maverick-embedded.co...

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Yes, the RUNSTDBY bit  is set.

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It still smells like some RUNSTDBY / ONDEMAND clock configuration issue. Double-check the clock tree and EVSYS CHANNELn register to ensure clocks/devices are running in standby.

 

Failing that, I'm out of ideas.

 

Steve

Maverick Embedded Technologies Ltd. Home of Maven and wAVR.

Maven: WiFi ARM Cortex-M Debugger/Programmer

wAVR: WiFi AVR ISP/PDI/uPDI Programmer

https://www.maverick-embedded.co...