samd21 PLL vs DFLL

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In my application my samd21 is in standby sleep most of the time, only waking up to perform some operation and then go right back to sleep.  I currently have my clock configured using the 32 kHz external oscillator (XOSC32), feeding DFLL at 48 MHz.  I am curious the tradeoff if I use the PLL sourced from the external 32 kHZ oscillator running at 48 MHz.  I have anecdotal read that the PLL is more stable but takes more power.  Is the PLL more stable?

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Hi,

 

photonthunder. We tried both PLLs (DPLL and DFLL) of SAMD21 and found these differences

 

Startup Time: 

  DPLL 1.2/2 ms   (typ/max)

  DFLL 0.2/0.5 ms (typ/max)

 

And yes, the DPLL ist more stable, we switched from DFLL to DPLL because of UART communication problems. Unfortunately DPLL starts slower and needs more power.

 

regards

 

spachner

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Thanks for the information, we did switch to DPLL as well, but I had not noticed any real differences in our application where the device will sleep for 20-30 seconds at a time and then just be on typically for several hundred milliseconds.