SAMD11 VDDCORE VREG and BOD12

1 post / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The SAMD11 VDDCORE supply voltage (provided by the internal VREG) doesn't have a dedicated external pin for decoupling (contrary to most of the larger chips, like SAMD21 for example).

 

I would love to have a way of accessing the VDDCORE for additional decoupling and/or for measuring. With Atmel studio 7 installed, in the directory Atmel\Studio\7.0\packs\atmel\SAMD11_DFP\1.1.81\atdf there is a file named ATSAMD11D14AM.atdf and on lines 528-547 I see some things of interest. Most notably on 529: <signal group="CAPLESS_VDDCORE" function="VREG" pad="PA02"/> That seems to indicate the possibility of somehow exposing VDDCORE on PA02. Does anyone have any insight into this? Unfortunately the datasheet seems to be severely lacking regarding documentation on VREG and BOD12.

 

I'm experimenting with low power standby sleep mode, and the SAMD11 seems to be getting unstable. I followed the suggestion of disabling BOD12 when going to sleep, and re-enabling it immediately after waking up (datasheet 38.2.4 section 1). This sort of works, but only if the CPU is running slowly. If it's running at 48MHz, if it was sleeping for less than about 2ms, it will sometimes fail to wake up (it sometimes hangs/freezes). I'm also running the standby function from RAM and doing a couple reads from FLASH before returning to running from Flash (SAM D11 Silicon Errata section 3, applying "Work around" 2).

 

Note that I do seem to have a solution for reliably sleeping and waking up after any length of time. It's working reliably by reducing the GCLK0 (main clock) down to 8MHz or slower. However, this means either running slower (obviously) or taking longer to go to sleep and wake back up (switching to 8MHz, turning off DFLL48, sleeping, turning on DFLL48, and switching back to 48MHz).

 

So I'm not really searching for info on sleeping; I'm just describing the conditions it's in when it freezes, and my desire to scope and/or decouple VDDCORE.

 

In addition to getting electrical access to VDDCORE, I'm also looking for any information on VREG and BOD12 and their configuration registers.

 

*edit* Added the below information:

 

Based on the datasheet errata suggestion (38.2.4 section 1), I'm assuming the BOD12 register is a 32-bit register at address 0x40000838. Reading the reset default value of the register, I get 0x0010000A, which makes me wonder why the suggested method of disabling/enabling it also changes other bits. I'm curious what those other bits are.

 

Judging from the SAMD21 datasheet, I'm assuming the VREG register on the SAMD11 is a 16-bit register at 0x4000083C. It's default value at reset seems to be 0x0602.

 

I've asked Microchip about this, especially since the datasheet actually references VREG.ENABLE, VREG.LEVEL, VREG.VDDMON, and VREG.RUNSTDBY, but totally fails to even document the VREG register.

Last Edited: Thu. May 5, 2022 - 11:01 PM