The SAM3X datasheet states that :
The SAM3X8ERT features three GPNVM bits that can be cleared or set respectively through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC0 User Interface.
There is no GPNVM bit on Flash 1.
I guess the GPNVM bits are located in the EEFC0 controller, neither in flash 0 or flash 1. Right ?
From ASF source code we can set GPNVM bits using the "efc_perform_command" function.
This function calls "efc_perform_fcr" surrounded with "cpu_irq_save" and "cpu_irq_restore".
Are "cpu_irq_save" and "cpu_irq_restore" really necessary to set or clear GPNVM bits ?
Thanks in advance for your help.