SAM port driver bidirectional

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Hello all,

 

I am using PORT - GPIO pin control (driver) with ASF 6.2 and I am trying to implement a bidirectional GPIO on a SAMD21 dev board.

My method of doing this feels a bit cumbersome and I am wondering if there is a better way.

Mainly is there a way to do something like DDRA = 0xFF for outputs and DDRA = 0x00 for inputs?

 

 

Here are my write and read routines...

 

Write_Routine()

{

  struct port_config pin_conf;

  port_get_config_defaults(&pin_conf);

 

  pin_conf.direction = PORT_PIN_DIR_OUTPUT;

  port_pin_set_config(MY_GPIO, &pin_conf);

  port_pin_set_output_level(MY_GPIO, TRUE);

 

}

.

.

.

 

bool Read_Routine()

{

  bool value;

  struct port_config pin_conf;

  port_get_config_defaults(&pin_conf);

 

  pin_conf.direction = PORT_PIN_DIR_INPUT;

  port_pin_set_config(MY_GPIO, &pin_conf);

  value = port_pin_get_input_level(MY_GPIO);

 

return value;

}

 

 

Last Edited: Thu. Oct 15, 2015 - 11:34 PM
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	if (direction == OUTPUT) {
		port_base->DIRSET.reg = pin_mask;
		} else {
		port_base->DIRCLR.reg = pin_mask;
	}

 

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Well, you could simplify the ASF version by making the config global and not recreating & re-initialising it each time

 

Quote:

struct port_config pin_conf;

 

Init_Routine()

{

   port_get_config_defaults(&pin_conf);

}

 

Write_Routine()

{

  pin_conf.direction = PORT_PIN_DIR_OUTPUT;

  port_pin_set_config(MY_GPIO, &pin_conf);

 

  port_pin_set_output_level(MY_GPIO, TRUE);

}

 

bool Read_Routine()

{

  bool value;

 

  pin_conf.direction = PORT_PIN_DIR_INPUT;

  port_pin_set_config(MY_GPIO, &pin_conf);

 

  value = port_pin_get_input_level(MY_GPIO);

 

  return value;

}

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Note also that using ASF in general doesn't preclude direct register access in special cases like this where you need something that ASF doesn't do (well)

 

So you could also have something like:

struct port_config pin_conf;

 

Init_Routine()

{

   port_get_config_defaults(&pin_conf);

   port_pin_set_config(MY_GPIO, &pin_conf);

}

 

Write_Routine()

{

  port_base->DIRSET.reg = pin_mask;

 

  port_pin_set_output_level(MY_GPIO, TRUE);

}

 

bool Read_Routine()

{

  bool value;

 

  port_base->DIRCLR.reg = pin_mask;

 

  value = port_pin_get_input_level(MY_GPIO);

 

  return value;

}

 

 

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Of course, this all assumes that it really is just the direction that you need to change; the SAMD21 has a whole bucketload of port configuration options - not all of them are going to make sense (or even be valid?) in both input & output modes ... 

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Do you really need to switch at all?

 

Can't you just use 

 

PORT_PIN_DIR_OUTPUT_WTH_READBACK 

The pin's output and input buffers should be enabled, so that the pin state can be set and read back.

 

http://asf.atmel.com/docs/3.16.0...

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Note that the name of the "Direction" (sic) register is rather misleading:

 

 

It would be more accurate to call it the "Output Enable" register...

 

Sadly, there isn't an Open-Drain option for the output driver.

 

frown

 

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Fascinating.  The datasheet claims that Open drain is possible (in the text), and mentions a WRCONFIG.ODRAIN bit (also in the text), but the bit and the mode are completely absent from the more detailed "register descriptions."

Sam3X has open drain via the "MultiDriver" registers, but it's GPIO is essentially a completely different peripheral than the SAMD chips...

 

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Well, you could simplify the ASF version by making the config global and not recreating & re-initialising it each time

Yes this works and it simplifies things a bit.  Though, for some reason, I prefer direct register access like the older ATMega microcontrollers instead of calling out port config functions in ASF.

You brought up a good point with the PORT_PIN_DIR_OUTPUT_WTH_READBACK setting.  I am looking into how to disable the output driver.  An open drain would be nice but it sounds like it might not be possible with the SAMD chips. 

 

 

 

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westfw wrote:
The datasheet claims that Open drain is possible (in the text), and mentions a WRCONFIG.ODRAIN bit (also in the text), but the bit and the mode are completely absent from the more detailed "register descriptions."

Yes, I seem to remember noticing that ...

 

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