SAM D20: DFLL48 in closed or open loop mode?

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I'm using an external 32.768kHz crystal that I will use for RTC too (so it should have a high accuracy). I'm trying to use it as the reference for DFLL48 in closed-loop mode. As I described in another post, unfortunately the initialization sometimes hangs forever because the DFLL fine lock isn't never reached.

 

So I'm asking what are the real differences between open and closed loop. In open loop I shouldn't need to wait for fine lock, so it should be a safer choice. What are the problems with the open loop mode?

 

I don't think I need high accuracy for the clock. I only use SERCOM in UART mode with 115200bps baudrate.

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This happened on my SAMD21. The fix was to set up the watchdog to reboot the system if it didn't lock within about 1/4 sec. If it does lock, don't forget to disable the watchdog, otherwise it will shoot you down again

It seems to have always worked at the second attempt

The code is:

/* Sometimes the DFLL48M doesn't lock, set up the WDT to do a restart.
  Use GCLK1 (XOSC32K) as clock. Normal mode, 1/4 sec 
*/
  set_clkctrl(GCLK_CLKCTRL_GEN_GCLK1_Val, GCLK_CLKCTRL_ID_WDT_Val);
  WDT->CONFIG.bit.PER = WDT_CONFIG_PER_8K_Val;  /* 1/4 sec */
  while (WDT->STATUS.bit.SYNCBUSY)
    ;
  WDT->CTRL.bit.ENABLE = 1;
  while (WDT->STATUS.bit.SYNCBUSY)
  ;
  while(!SYSCTRL->PCLKSR.bit.DFLLRDY)  /* Wait for DFLL ready */
    ;
  while(!SYSCTRL->PCLKSR.bit.DFLLLCKF)  /* Wait for DFLL fine lock */
    ;
  WDT->CTRL.bit.ENABLE = 0; /* watchdog off, so it doesn't kill me later */
  while (WDT->STATUS.bit.SYNCBUSY)
    ;
  SystemCoreClock = DFLLMULT * DFLL_REF_FREQ;  /* New GCLK_MAIN */

 

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Yes, this is the last solution that I'm going to try. I already use watchdog in the project, but I enable it after system_init() because of many loops during clock sync. I'll try to enable it before system_init().

 

Anyway this is a workaround, not a real solution. We hope the second time the DFLL locks, but are we sure? What is the reason the fine lock sometimes doesn't happen?

 

Even in your case you experienced this issue after cutting out and reapply the supply after some seconds?

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I couldn't find any electrical characteristic for DFLL48M used in open-loop mode. Mainly I'm interested in accuracy and variation of the frequency with temperature and supply voltage. Where are those characteristics? How could I use DFLL48M in open-loop without knowing anything about its performance?

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pozzugno wrote:
Yes, this is the last solution that I'm going to try. I already use watchdog in the project, but I enable it after system_init() because of many loops during clock sync. I'll try to enable it before system_init().

You're right about the crudity of the fix

I put the DFLL48M setup right at the start of the program, using the watchdog. In this way one loses as little time as possible if it has to reboot

In Table 37-53 and -54 of the datasheet it specifies a maximum lock time in closed-loop mode of 500µsec. On could use a loop counter instead of the WDT for the wait delay, so speeding up the boot process

At the moment I'm about 600km away from my test system, and will see how often it has to restart on returning home

Jerry