I'm wondering how many people are running their SPI bus at very low speeds, say, less than 1mhz. It seems (at least to my perception) that most people run the SPI at a very high speed and have the processor run in a busy loop while the transfer finishes. However, this kind of speed seems unnecessary in alot of AVR applications, unless perhaps you have a large number of SPI devices. Case in point: an Atmel SPI dataflash chip takes 20ms to erase and program a page, however, transferring the full page over SPI at 250khz only takes 16ms. The SPI running full time would easily keep the page buffers full. At such a low speed an interrupt driven approach becomes feasible (I wrote a full-duplex transfer routine in C that takes 62 cycles in the ISR). My busy loop transfer at 8mhz takes 49 cycles. Is this a worthwhile tradeoff? I would think that the lower speed could have significant EMC benefits at some applications.
Anyway, food for thought I guess.