RTOS for ARM AT91SAM7X512 with zigbit

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ZigBit stack from Atmel supports only state machine as a operating system.
There is a lot of RTOS available for this ARM processor.
Does anybody run ZIGBIT together with RTOS ?
For example: all zigbit stack is running as a one task - and it communicates with other tasks ?

Any other ideas ?

Last Edited: Fri. Oct 16, 2015 - 02:16 PM
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ZigBit is a module. Stack is called BitCloud.

I don't think I've ever seen anyone do this recently, but some early versions could work under FreeRTOS. I don't think this has changed, but there is official support and recommendations on how to do that.

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Thanks Alex,

Sorry for my mistake in the naming.

Do you know any open source zigbee stack for linux ?
I am asking because I also consider to use SAM9 from Atmel ?

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I think there is only one attempt at making open ZigBee stack - by FreakLabs. But their code has a long way to go before it becomes a real stack. And I'm pretty sure they've never certified it even once, and this is expensive and chances are you are not gonna pass on the first time.

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alexru wrote:

I don't think I've ever seen anyone do this recently, but some early versions could work under FreeRTOS. I don't think this has changed, but there is official support and recommendations on how to do that.

In the BitCloud for SAM7 I found lot of the code to add support for FreeRTOS. Does there any manual how to run bitcloud with this OS?

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Where exactly do you see this code?

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Please start from BitCloud/Components/HAL
And then search for FREE_RTOS.
for example:

/****************************************************************
  RF interrupt service routine.
****************************************************************/
void irqRfHandler(void)
{
#if defined(PLATFORM_SAM7X_EK_RF2XX) || defined(PLATFORM_CUSTOM_1) || defined(PLATFORM_CUSTOM_2)
  #if defined(FREE_RTOS)
    portSAVE_CONTEXT();
  #endif
#endif

  phyDispatcheRfInterrupt();

#if defined(PLATFORM_SAM7X_EK_RF2XX) || defined(PLATFORM_CUSTOM_1) || defined(PLATFORM_CUSTOM_2)
  #if defined(FREE_RTOS)
    /* End the interrupt in the AIC. */
    AT91C_BASE_AIC->AIC_EOICR = 0;

    portRESTORE_CONTEXT();
  #endif
#endif
}
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This code is a legacy, it was written in 2008 or so to run MAC layer only and never been tested since.

But if you run entire stack in one task, then this is all you really need. There is no sample projects for it, obviously.

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Doesn't one need a $$$ license from the ZigBee alliance to sell any product claiming to conform to that proprietary standard?

(for the unitiated, ZigBee is to IEEE 802.15.4 as IP is to IEEE 802.3. ZigBee is not a synonym for 802.15.4)

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stevech wrote:
Doesn't one need a $$$ license from the ZigBee alliance to sell any product claiming to conform to that proprietary standard?
Only if you want to put ZigBee logo.

How is this relevant to the topic of this conversation at all?

stevech wrote:
ZigBee is not a synonym for 802.15.4)
Nobody said the opposite.

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Hi,

I am getting this abort when I try to run BiCloud with freeRTOS

 Data abort at 0x0010767F
 ARM core is source of the abort status.
 Word size (32-bit) abort access to misaligned address.
 Data read abort access.
 Stack pointer before exception. SP = 0x00206DB0
 Data abort link register. LR = 0x001084D4
 Status register before exception. CPSR = 0xA000003F
 Abort instruction has LR-8 address.
 CPU registers r0-r12:
0x00109A14 0x0010767F 0xFFFFFFFC 0xFFFFFFFF
0x00000003 0x00000000 0x06060606 0x07070707
0x08080808 0x09090909 0x10101010 0x11111111
0x00000003
 Stack memory dump:
0x00000000 0x0010767F 0x0010767F 0x04040404 0x00000000 0x002111B8 0x03030303
0x00000000 0xA5A5A5A5 0xA5A5A5A5 0x00000001 0x002111B8 0x00000003 0x00000000
0x00207000 0x00000000 0x00201040 0x00201040 0x00206DE8 0x00201038
*********************************************

Could you please explain me how to read all this data ?
the same BitCloud binary lib is working correctly.

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Instruction that caused the abort is at LR-8 = 0x001084D4-8 = 0x001084CC,

Use disassembler to find out what this instruction is and to which part (BitCloud or FreeRTOS) it belongs to.

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Hi,
Thanks,

It seems that this is part of the halAddTimer function:

001084c4:   bne.n 0x1084cc 
001084c6:   ldr r3, [r0, #8]
001084c8:   cmp r3, r2
001084ca:   bls.n 0x1084d6 
 48         for (it = *head; it; it = it->service.next)
001084cc:   ldr r3, [r1, #0]
001084ce:   adds r6, r1, #0
001084d0:   cmp r3, #0
001084d2:   bne.n 0x10846c 
001084d4:   b.n 0x1084e4 
001084d6:   ldr r4, [sp, #4]
 59         if (it == *head)
001084d8:   adds r3, r1, #0
001084da:   cmp r1, r7
001084dc:   bne.n 0x1084e4 
 61           newTimer->service.next = *head;
001084de:   str r1, [r0, #0]
 62           *head = newTimer;
001084e0:   str r0, [r4, #0]
001084e2:   b.n 0x1084e8 
 66           prev->service.next = newTimer;
001084e4:   str r0, [r6, #0]
 67           newTimer->service.next = it;
001084e6:   str r3, [r0, #0]
 69       }

I will debug it more deeply in next days.

Thanks!

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So for some reason r1 became unaligned. And from the dump above you can see that r1 is 0x0010767F, which does not look like a pointer to a RAM location and it is definitely not aligned. Something damaged this register.

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Is it possible that above problem happens with incorrect usage of the thumb and arm mode ?
Is it possible that this problem happens because bitcloud is not prepared to do not work in thumb instruction set ?
(It should work in supervisor mode ?)

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None of this is possible. BitCloud by default uses mix of thumb and arm modes.

You'll have to be more specific. Does this happen only under FreeRTOS? At what point it happens? Immediately? Randomly?

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It happens only with FreeRTOS.

I am trying to debug this with JTAG (to break at specific instruction) but in that case it not happen (everything works correctly).

I am not sure if I correctly setup OS:
I create two simple tasks which prints only debug on the serial line - it works correctly - when I enable third bitcloud task my problems start to happen.
It also occur if I run only bitcloud task (so switching task should not appear)
It happens at the beginning more less after call to

ZDO_StartNetworkReq

Function returns but callback is never called
I am also getting IRQ from

irqRfHandler
  phyDispatcheRfInterrupt();

When I try to run with SAM-ICE JTAG it works correctly.

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Some additional info:
Exceptions do not happen in the same place - but all exceptions happens with register r3 and value 0x0001.
Maybe this is a problem with some ISR which do not save r3 register?

 Data abort at 0x00000001
 ARM core is source of the abort status.
 Word size (32-bit) abort access to misaligned address.
 Data read abort access.
 Stack pointer before exception. SP = 0x00204400
 Data abort link register. LR = 0x00107BAC
 Status register before exception. CPSR = 0x4000003F
 Abort instruction has LR-8 address.
 CPU registers r0-r12:
0x00107E88 0x00106B1B 0x00000000 0x00000001
0x0000000A 0x00211178 0x06060606 0x07070707
0x08080808 0x09090909 0x10101010 0x11111111
0x00000003
 Stack memory dump:
0x00000000 0x00106B1B 0x00106B1B 0x04040404 0x05050505 0x00106B1B 0x03030303
0x00000000 0xA5A5A5A5 0xA5A5A5A5 0x002110E8 0x00000060 0x00000000 0x00000000
0x00204650 0x00000000 0x0020100C 0x0020100C 0x00204438 0x00201004
*********************************************

And code for this exception:

00107b9c:   bne.n 0x107ba0 
205       		pxList->pxIndex = pxItemToRemove->pxPrevious;
00107b9e:   str r2, [r3, #4]
208       	pxItemToRemove->pvContainer = NULL;
00107ba0:   movs r2, #0
00107ba2:   str r2, [r0, #16]
209       	( pxList->uxNumberOfItems )--;
00107ba4:   ldr r2, [r3, #0]
00107ba6:   subs r2, #1
00107ba8:   str r2, [r3, #0]
212       }
00107baa:   ldr r0, [r3, #0]
00107bac:   pop {r1}
00107bae:   bx r1
          timerHandler:
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I don't know why BitCloud might not work under FreeRTOS. Sorry I can't help you here.

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I think I know. this is probably problem with default fiq-handler:

/*------------------------------------------------------------------------------
 *- Function             : fiq_handler
 *- Treatments           : FIQ Interrupt Handler.
 *- Called Functions     :
 *------------------------------------------------------------------------------*/
fiq_handler:
	/* Adjust LR_irq and save in FIQ stack*/
		sub		 lr, lr, #4
		stmfd    sp!, {lr}

    /*- Save r0 and SPSR in FIQ stack */
        mrs      r14, SPSR
        stmfd    sp!, {r0,r14}

    /* Read the AIC Fast Interrupt Vector register to clear the interrupt */
        ldr		 r14, =AT91C_BASE_AIC
        ldr      r0 , [r14, #0x00000104]
        str      r14, [r14, #0x00000104]

    /*- Save scratch/used registers and LR in FIQ Stack */
        stmfd    sp!, {r1-r7, r12, r14}

    /*- Branch to the routine pointed by the AIC_FVR */
        mov      r14, pc
        bx       r0

    /*- Restore scratch/used registers and LR from FIQ Stack */
        ldmia    sp!, {r1-r7, r12, r14}

    /*- Restore SPSR_irq and r0 from FIQ stack */
        ldmia    sp!, {r0,r14}
        msr      SPSR_cxsf, r14

    /*- Restore adjusted  LR_irq from FIQ stack */
        ldmia    sp!, {lr}

    /* Return from Fiq interrupt */
		movs	 pc, lr

It is taken from halFreerosBoot.s - but I think it should be modified to support freeRTOS.

Any ideas how to fix it ?
I mean how to replace above fiq handler with handler working with freeRTOS ?

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OK. FreeRTOS starts to work with the BitCloud.
It is not stable but connected with one child :)

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Was there a definitive reason? Can you share?

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jump to the FIQ handler should look like IRQ:

	ldr   pc, [pc,#-0xF20]						    /* FIQ - _fiq				*/

I took this from the Atmel ARM7x datasheet.

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How do you think stack size should be for the BitCloud task ?

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BitCloud does not allocate a lot of stuff on the stack, 500 bytes should be more than enough.

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