RTC and not resetting its clock during RESET

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The RTC peripheral of most Atmel SAMD products does not get automatically reset expect a power-on reset.  This is clearly documented.

The clock of RTC is likewise not reset, and the GCLK configuration from which the RTC clock is derived is supposedly not reset, either.

 

So... What happens if the GCLK supplying the RTC has a more complex configuration, where it's input comes from yet another GCLK that requires significant setup.  Say you want a 8MHz RTC clock on a dedicated GCLK4, derived from the 48MHz system clock (GCLK1) that is in turn sourced from the 48MHz DFLL, in turn controlled by XCLK32?

 

There is a problem over in Arduino land like this: https://forum.arduino.cc/index.p... The SAMD21 appears to become unresponsive after reset if the RTC was configured.  It looks like it's hanging somewhere, probably waiting for Sync from something, somewhere.

 

This becomes unresponsive on the 2nd reset (maybe "becomes unresponsive"?)

 

//  This is to test the strange behaviour with the GCLK setup.

// Sync GCLK
static __inline__ void syncGCLK() __attribute__((always_inline, unused));
static void syncGCLK() {
  while (GCLK->STATUS.bit.SYNCBUSY == 1);
}

void setup() {
  // put your setup code here, to run once:
    Serial.begin(9600);
  setGCLK();  
}

void loop() {
  // put your main code here, to run repeatedly:
   Serial.println("Do something");
   delay(2000);
}


// ###########################################################################
// setGCLK() Set-up of GCLKs to produce 8 MHz for (RTC, ADC) 
// ###########################################################################
void   setGCLK(){

  // Setup GCLK 4 to produce 8 MHz from 48 MHz clock generator 
  GCLK->GENDIV.reg = GCLK_GENDIV_DIV(1) |          // 48 MHz / 6 = 8 MHz
                     GCLK_GENDIV_ID(4);            // Assign to GCLK4
                     syncGCLK();                   // Wait for synchronization
  GCLK->GENCTRL.reg = GCLK_GENCTRL_IDC |           // Force to 50:50 mark space
                      GCLK_GENCTRL_GENEN |         // Enable GCLK4
                      GCLK_GENCTRL_SRC_DFLL48M |   // Set the 48MHz clock source
                      GCLK_GENCTRL_ID(4);          // Select GCLK4
                      syncGCLK();   
                      // Sync

 // Select GCLK4 and cofigure to clock RTC at 8 MHz
  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN |         // Enable GCLK
                     GCLK_CLKCTRL_GEN_GCLK4 |     // Select GCLK4 source DOES NOT WORK
 //                  GCLK_CLKCTRL_GEN_GCLK0 |     // Select GCLK4 source DOES  WORK
  //                  GCLK_CLKCTRL_GEN_GCLK1 |     // Select GCLK1 source DOES  WORK       
                      GCLK_CLKCTRL_ID_RTC;         // Feed to RTC
                      syncGCLK();                  // Sync
                      RTC->MODE2.CTRL.bit.SWRST = 1;                       // Software reset the RTC
while (RTC->MODE2.STATUS.bit.SYNCBUSY);              // Wait for synchronization ...
while(RTC->MODE2.CTRL.bit.ENABLE);                   // Wait for the RTC to become disabled
  }
// ###########################################################################