Rise time for AVR GP port pins

Go To Last Post
8 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I'm looking for the documented rise times on AVR general purpose port pins. As an example, in the ATMega644 datasheeet, I've found rise times documented for External Clock, TWI, and SPI pins. But, I can't find the rise time for general purpose port pins.

Perhaps it's documented and I'm not finding it. For example, I had done a fair bit of searching for the port pins' output impedance, but finally found that data in the I/O pin output voltage vs. source/sink current graphs.

Thanks for any help!

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

you would need to know what load is on the pin.

Go electric!
Happy electric car owner / builder

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

And be able to model the output circuit. You could use a buffer with known characteristics, or one that you could model.

Leon

Leon Heller G1HSM

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Yes, it's a good point that rise and fall times are dependant on the load. I suppose the typical rise times quoted for various-speed CMOS logic families is based on some standard load, such 100 ohms and 50pF. The AVR datasheet gives a formula for the TWI (SDA and SCL) rise time of 20+(0.1 x load-capacitance-in-pF) ns, which of course neglects the resistance and inductance of the load. Is there any particular formula for computing the rise time for a GP pin, or is just sometime one measures.

As an example, the output impedance of the AVR is about 25ohms. I'm looking to output a signal to a series resistor of 25ohms (which delays rise time) into 50ohm PCB trace then into a 50ohm cable to a high-impedance device. The series resistor will handle the reflections of the signal. How could I go about computing the expected rise time at the series resistor?

Edit: perhaps it's better to make a simpler example. Say a port pin hooked to a "long" PCB transmission line of 50ohm impedance. "Long" being long enough that the any reflections occurs after output pin rises to full, initial voltage. With a Vcc of 5V, at time 0, the output will start to rise from 0V to an initial voltage of 3.3V (the voltage created by the voltage divider of the 25ohm output impedance and the 50ohm impedance line). Are there any specs published on the AVR that will help calculate that rise time from 0V to 3.3V?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I don't know of any. But I will tell you that I would be wary of a design that depended on the output slewrate of an AVR (or any uP) output pin. What happens if they change the driver on you? Your answer is: Well I'd have to change my circuit. Why then, wouldn't you avoid this question in the first place and, since your circuit is somehow sensative to rise time, design a buffer that delivers the proper rise-time independant of the uP.

Go electric!
Happy electric car owner / builder

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

What you need is the IBIS model. This is a human-decipherable text file intended for use in simulation tools, you can download it from Atmel. Plug that and the PCB into your simulation tool and it should give you a pretty good guess. Remember to pick the RIGHT IBIS file - there are several for the same part, describing different silicon versions.

[Rising Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
| time           V(typ)              V(min)              V(max)
|
  0.000S         0.000V              0.000V              0.000V
   0.50nS         1.00mV              0.30mV              2.10mV
   1.00nS        -7.23mV              2.93mV            -35.74mV
   1.50nS       -31.90mV            -28.31mV              0.17V
   2.00nS         0.23V             -31.75mV              1.01V
   2.50nS         0.59V              91.28mV              1.76V
   3.00nS         0.90V               0.21V               2.12V
   3.50nS         1.22V               0.39V               2.65V
   4.00nS         1.43V               0.58V               3.17V
   4.50nS         1.60V               0.70V               3.48V
   5.00nS         1.94V               0.85V               3.74V
   5.50nS         2.22V               0.94V               3.83V
   6.00nS         2.50V               1.03V               3.88V
   6.50nS         2.74V               1.14V               3.92V
   7.00nS         2.86V               1.24V               3.94V
   7.50nS         2.99V               1.42V               3.97V
   8.00nS         3.07V               1.60V               3.98V
   8.50nS         3.10V               1.70V               3.99V
   9.00nS         3.13V               1.80V               4.00V
   9.50nS         3.17V               1.96V               4.00V
  10.00nS         3.19V               2.06V               4.01V
  10.50nS         3.20V               2.13V               4.01V
  11.00nS         3.21V               2.20V               4.01V
  11.50nS         3.23V               2.27V               4.02V
  12.00nS         3.24V               2.32V               4.02V
  12.50nS         3.24V               2.35V               4.02V
  13.00nS         3.25V               2.39V               4.02V

This is what it would look like with 5V VCC driving a 50 ohm load directly. Into 2k it's faster, about 4ns.

If you need to drive 50 ohm coax with >1V swing you'll need a line driver.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

sgomes, thanks for the thoughts. If the output slew rate is specified (somewhere) for a processor, then I can depend upon it for that design. My main issue for knowing the rise time is I can then compute how long I can make a PCB trace before I have to worry about reflections leading to inadequate signal integrity. The ATMega644 datasheet kindly supplies rise/fall times for TWI and CLKOUT so I can make those calculations. However, I was hoping (er, still hoping) that rise times are documentated somewhere for GP pins.

For example, the rise time of SDA is 20+ns (relatively slow). If I design for a 1/4 TEL as a boundary between low-speed and high-speed techniques, then I have have signals 30 FR4 inches long without adding high-speed design techniques. One the other hand, if a GP rise time is 2ns, then 1/4TEL is only 3in on a PCB. In such cases, I'd more often need to ensure proper path impedance and termination depending upon the load placement. And is rise time is 0.5ns, well you get the idea, then 1/4TEL = 0.75in.

Last Edited: Tue. Jul 10, 2007 - 12:26 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

KKP, excellent -- that's the data that I was looking for. I'll search for it on atmel's site.

Thanks very much, Freaks come through again!