The new AVRs with dual/triple-priority interrupts no longer clear the global Interrupt Enabled flags in the CPU status register when you enter an ISR, or re-set it when the RETI instruction is done. Instead, there is a new register CPUINT.STATUS that has bits for each level of interrupt, and entry/RETI sets/resets those.
However, CPUINT.STATUS is described as READ-ONLY. Does that mean that there is no "convenient" way to re-enabled interrupts within an ISR? (yes, I know that that's not a particularly good idea. I also know that it is occasionally done anyway...)