Raspberry Pi is now a microcontroller

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The Rapsberry Pi Blog wrote:
Today, we're launching our first microcontroller-class product: Raspberry Pi Pico.

Priced at just $4, it is built on RP2040, a brand-new chip developed right here at Raspberry Pi.

 

 

https://www.raspberrypi.org/blog/raspberry-pi-silicon-pico-now-on-sale/

 

  • Dual-core Arm Cortex-M0+ @ 133MHz
  • 264KB  on-chip RAM
  • Support for up to 16MB of off-chip Flash memory via dedicated QSPI bus
  • DMA controller
  • Interpolator and integer divider peripherals
  • 30 GPIO pins, 4 of which can be used as analogue inputs
  • 2 × UARTs, 2 × SPI controllers, and 2 × I2C controllers
  • 16 × PWM channels
  • 1 × USB 1.1 controller and PHY, with host and device support
  • 8 × Raspberry Pi Programmable I/O (PIO) state machines
  • USB mass-storage boot mode with UF2 support, for drag-and-drop programming

 

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Last Edited: Thu. Jan 21, 2021 - 10:19 AM
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Does it have Arduino support? (rhetorical question)

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i'm a bit confused it state :

  • 30 GPIO pins, 4 of which can be used as analogue inputs

But the text say :

Raspberry Pi on its own does not support analogue input  

 

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your first quote is for the new RPi microcontroller; the second quote refers to the original RPi - it is given as one of its limitations, and justification for the new chip.

 

EDIT

 

Maybe this goes to show that calling it "Rasperry Pi" was a poor choice - it's such a different beast that it really should have a distinct name ?

 

frown

 

Maybe we should call it the "Raspberry pip" ... ?

 

wink

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Last Edited: Thu. Jan 21, 2021 - 11:41 AM
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No internal flash, it seems.

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Indeed.

 

Presumably, some of that "264KB  on-chip RAM" gets used for code execution?

 

I wonder if it's 8K for execution, and then the other 256K for "data"?

 

Or vice-versa? surprise

 

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Kartman wrote:

Does it have Arduino support? (rhetorical question)

 

There is an official Nano-sized wireless board available soon, so presumably yes: : https://blog.arduino.cc/2021/01/...

 

I'm more interested to see whether it has FreeRTOS support, to manage the two cores.

 

I'm a little disappointed with the selection of peripherals. Actually, what I mean is, it doesn't have a CAN bus controller. And no on-chip flash, so an external chip is mandatory.

 

 

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or 8 K USB buffer RAM, and the rest is normal 256k RAM (both code and data).

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Nice performance per watt, which is likely due to the 40nm process.  Dormant (the lowest power mode) consumption is rather high at ~200uW.  The datasheet doesn't state how much lower that goes with MEMPOWERDOWN, so there may yet be hope for low-power battery operation.  I'm a bit surprised the chip only has USB full-speed (12Mbps) support, when high-speed would only take a tiny bit more die area.  With the PIO units and the relatively large 256kB SRAM, I could see it being used for a nice little logic analyzer.

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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awneil wrote:

Indeed.

 

Presumably, some of that "264KB  on-chip RAM" gets used for code execution?

 

I wonder if it's 8K for execution, and then the other 256K for "data"?

 

Or vice-versa? surprise

 

 

The 8kB is on a different internal bus, and is recommended for the processor stack.

For code, it has an XIP cache: "External Flash is accessed via the QSPI interface using the execute-in-place (XIP) hardware" (datasheet s. 2.6.3)

"The cache is 16 kB, two way set-associative, 1 cycle hit. It is internal to the XIP subsystem, and only affects accesses to
XIP flash, so software does not have to consider cache coherence, unless performing flash programming operations. It
caches reads from a 24-bit flash address space, which is mirrored multiple times in the RP2040 address space, each alias
having different caching behaviour. The eight MSBs of the system address are used for segment decode, leaving 24 bits
for flash addressing, so the maximum supported flash size (for XIP operation) is 16MB."

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Here's the SRAM details:

"There is a total of 264kB of on-chip SRAM. Physically this is partitioned into six banks, as this vastly improves memory
bandwidth for multiple masters, but software may treat it as a single 264kB memory region. There are no restrictions on
what is stored in each bank: processor code, data buffers, or a mixture. There are four 16k x 32-bit banks (64kB each) and
two 1k x 32-bit banks (4kB each)."

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Does it have a Basic compiler smiley

 

JC

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DocJC wrote:
Does it have a Basic compiler
The usual trend these days (when not doing C/C++) actually seems to be to provide micros with some form of Python (which is a bit like "BASIC on steroids"  anyway! ;-)

 

EDIT: didn't take long to find... https://magpi.raspberrypi.org/ar...

 

Last Edited: Thu. Jan 21, 2021 - 04:49 PM
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ralphd wrote:
The 8kB is on a different internal bus, and is recommended for the processor stack.

 

That's interesting, having the stack in a dedicated memory bus. I wonder how much the average performance gain is? Maybe the bus is wider/faster?

Last Edited: Thu. Jan 21, 2021 - 05:01 PM
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El Tangas wrote:

ralphd wrote:
The 8kB is on a different internal bus, and is recommended for the processor stack.

 

That's interesting, having the stack in a dedicated memory bus. I wonder how much the average performance gain is? Maybe the bus is wider/faster?

 

The datasheet has a pretty good description of the architecture.  It also reads like something written by an anglophone, which I find quite nice.

 

"There are four 16k x 32-bit banks (64kB each) and two 1k x 32-bit banks (4kB each)."

"The next two 4kB regions (starting at 0x20040000 and 0x20041000 ) are mapped directly to the smaller, 4kB memory banks.
Software may choose to use these for per-core purposes, e.g. stack and frequently-executed code, guaranteeing that the
processors never stall on these accesses."

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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That is all sorts of interesting :-)

 

update: add a link

 

https://hackaday.com/2021/01/20/raspberry-pi-enters-microcontroller-game-with-4-pico/

Last Edited: Thu. Jan 21, 2021 - 08:28 PM
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though a ROM

RP2040 Datasheet

[page 144]

2.6.1. ROM

[summary]

  • first level boot
  • second level boot (external flash)
  • write external flash
  • USB MSC
  • utilities (floating point, etc)

[/summary]

Arm with ROM is somewhat common; one way to implement secure boot.

Arm without flash :

  • Ambiq Apollo4 (very low current, MRAM)
  • VORAGO (up to 200C, radiation resistant)

Flash is temperature sensitive and fails due to some excessive radiation (solar flares, GCR, Van Allen belt high energy electrons, Fukushima Daiichi robots, Mars ...)

 


User Interface? | Page 2 | AVR Freaks

The challenges and evolution of CubeSat electronics - Embedded.com

Microcontrollers | VORAGO Products — VORAGO Technologies

RIP Opportunity | The Embedded Muse 368

 

"Dare to be naïve." - Buckminster Fuller

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ralphd wrote:
The datasheet has a pretty good description of the architecture.  It also reads like something written by an anglophone, which I find quite nice.

gchapman wrote:
RP2040 Datasheet

 

I'll be sure to read it. First impressions: it has (a lot) fewer than 1000 pages = good smiley

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Regarding Python:

 

So over my break between Christmas and New Years I had a few days off, and purchased two Python books. 

There still sitting on my desk next to me.

 

Python, the Complete Manual, hasn’t been to helpful yet.

Python Programming for Dummies, however, got me started, at least up through several chapters before I had to re-focus on work.

 

From my (very limited) introduction, it struck me as very similar to Basic.

 

Except it needs a lot more colons to end commands, which the Basic compiler doesn’t need.

 

And I’m used to reading code with If, Elseif, End If sections since the days of the Basic Stamp.

Of course Python eliminated the End If, using the un-indented code section to signify the End If.

My old brain still looks for the End If to signify closure of that section.

 

VB and Visual Studio both include a PC GUI.

For Python I had to go find an add on to provide the GUI for my simple PC test programs.

 

When I close a VB/VS program it just goes away.

Gone.

Disappears.

 

When I try, using multiple different constructs, to Close / End my GUI based Python program I still end up with one or two boxes on the screen that the User still has to close out manually… 

Several hours trying to figure out how to simply terminate a Python GUI program on the PC, without the remaining trash, left me frustrated.

 

Such is life.

 

If I want to play with the new Pi I guess I had best get over it and get on with the tutorial!

 

JC

 

 

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I like that the datasheet has a 'Programmer's Model' section for each peripheral with sample code and links to Github. Not just a list of registers and an uncertain wait for appnotes.

 

My sense is it's a better 'core' product technically than say ESP32 but lacking in peripherals, onboard flash and wireless. I guess they know their target market. Scope for v2 maybe.

 

You have to admire the 'splash' they've made with this though.

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DocJC wrote:
it struck me as very similar to Basic.

Really?!

 

What brand of "BASIC" are you thinking of?  

There are many things that call themselves "BASIC" yet bear precious little resemblance to the original language - or even to other things calling themselves "BASIC".

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Visual Basic / Visual Studio on the PC.

 

Bascom on the AVR.

Occassionally ZBasic on the AVR, but truth be told I usually use Bascom.

 

And, before you ask: No, I haven't used a Line Number or a Goto for the past 20 years... !

 

JC

 

Edit: Typo

 

 

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awneil wrote:
What brand of "BASIC" are you thinking of?  

 

Classification of imperative languages cheeky:

Has curly brackets -> similar to C

No curly brackets -> similar to BASIC

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Interesting that the standard peripherals (PIO, UART, I2C, SPI, I2S, etc) are software defined using generic IO hardware.

 

Datasheet p.323:

PIO is programmable in the same sense as a processor. There are two PIO blocks with four state machines each, that can independently execute sequential programs to manipulate GPIOs and transfer data. Unlike a general purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism, precise timing, and close integration with fixed-function hardware.

...

Each state machine, along with its supporting hardware, occupies approximately the same silicon area as a standard serial interface block, such as an SPI or I2C controller. However, PIO state machines can be configured and reconfigured dynamically to implement numerous different interfaces.

...

The four state machines execute from a shared instruction memory. System software loads programs into this memory, configures the state machines and IO mapping, and then sets the state machines running. PIO programs come from various sources: assembled directly by the user, drawn from the PIO library, or generated programmatically by user software.

From this point on, state machines are generally autonomous, and system software interacts through DMA, interrupts and control registers, as with other peripherals on RP2040. For more complex interfaces, PIO provides a small but flexible set of primitives which allow system software to be more hands-on with state machine control flow.

Maybe there'll be a CAN controller implementation eventually :)

Last Edited: Fri. Jan 22, 2021 - 01:00 AM
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Thanks for the link, looks like an interesting device.

 

Ordered a couple to see what I could do with them.

Happy Trails,

Mike

JaxCoder.com

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obdevel wrote:

Interesting that the standard peripherals (PIO, UART, I2C, SPI, I2S, etc) are software defined using generic IO hardware.

The 2 programmable IO blocks are in addition to the standard peripherals.  The standard peripherals are implemented in silicon and can't be re-programmed for other use.

S. 4.2 UART:

"RP2040 has 2 identical instances of a UART peripheral, based on the ARM Primecell UART (PL011) (Revision r1p5)."

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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What is the benefit of this over other arm cortex or esp? The pi zero has wifi and runs linux, which is a clear benefit, those zeros are fantastic little devices.

Last Edited: Fri. Jan 22, 2021 - 02:52 AM
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12oclocker wrote:
What is the benefit of this over other arm cortex or esp? The pi zero has wifi and runs linux, which is a clear benefit, those zeros are fantastic little devices.

 

The only thing special I see is the programmable IO device.  Although there is a lot of documentation and examples, it still is lacking important details.  For instance the OUT instruction says:

"Shift Bit count bits out of the Output Shift Register (OSR), and write those bits to Destination."  and "Bit count: how many bits to shift out of the OSR. 1…32 bits, 32 is encoded as 00000."

 

So if it can shift out 32 bits with one instruction, presumably it has a 32x PLL clocking the shift register.  And I think the bit timing is based on 32/bitcount, so shifting out 2 bits would be 16 shift register clocks per bit.  I'm not sure what would happen if you shifted 3 or 5 bits.  After digging through several of the examples I found this comment that bitcnt must be a factor of 32:

https://github.com/raspberrypi/p...

 

One thing it doesn't seem to support is starting the shift register, and having it continue to shift out bits while subsequent PIO instructions continue to execute.

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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ralphd wrote:

The 2 programmable IO blocks are in addition to the standard peripherals.  The standard peripherals are implemented in silicon and can't be re-programmed for other use.

S. 4.2 UART:

"RP2040 has 2 identical instances of a UART peripheral, based on the ARM Primecell UART (PL011) (Revision r1p5)."

 

Data headers say a quite modest UART max of 921600 baud, but the formula suggests  125/16 = 7.8125MBd is supported and 12MBd would be possible with overclock of 192MHz 

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DocJC wrote:

Except it needs a lot more colons to end commands, which the Basic compiler doesn’t need.

 

Diversion to Python rant: I know people love it, but to me a language that relies on white space for formatting is broken by design. I hate that...

 

And now, I return to our normal programming: regarding the QSPI flash: does the clock have spread spectrum options? Because without that, it's going to have some difficulty meeting EMI regulations if you use this in a production part. Ask me how I know...

 

Neil

 

Neil

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12oclocker wrote:
What is the benefit of this over other arm cortex

Note that it is a dual-core Cortex-M0+ - I don't think there's many others?

 

Also, executing from external flash is unusual for a Cortex-M0+

 

There are rumours abroad that ARM must have sunk some serious  cash into this - as a "fight-back" against the growth of RISC-V ...

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DocJC wrote:
My old brain still looks for the End If to signify closure of that section.
I remember when I first started doing things in Python this threw me completely too. However, after a while you learn to like this and I love the rigour it imposes on program structure. You simply don't get people posting Python code with stupid indentation all over the place making it virtually impossible to follow - all Python is laid out the same because it has to be and so it's much easier to read other people's Python programs as they all look similar (in C/C++ there's an attempt at this when "coding standards" are imposed but sadly not everyone adheres to the coding standard. In Python you simply don't get a choice). In fact Python has all kinds of other rules about structure and a good IDE will tell you about these as you go along. Talking of which:

DocJC wrote:
For Python I had to go find an add on to provide the GUI for my simple PC test programs
I hope it was "Pycharm" from Jetbrains you stumbled upon. I came across this early and it REALLY helped me. As I say there are various style guidelines for Python and PyCharm will advise you about these. There is a "Community" version for personal use:

 

awneil wrote:
Really?!

Why shocked? I've always thought that things like Microsoft Visual Basic was very similar to Python (or vicky-verky if you want to look at it that way).

 

The one thing in Python I have a bit of trouble with is how "self" is always out in the open whereas in C++ "this" is usually hidden. That can take a bit of getting used to. (though I know some people add "this" prefixes in C++ to make it clear what belongs to the class (I just prefer an 'm' prefix myself)).

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clawson wrote:
I've always thought that things like Microsoft Visual Basic was very similar to Python

That's why I asked what particular variant (or "deviant"?) of BASIC.

 

Visual BASIC bears very little resemblance to "traditional" BASIC.

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DocJC wrote:
Regarding Python:

To be fair, most of your troubles there seem to be with the environment - rather than Python itself.

 

I think it's true for any language that a good or bad environment can greatly help or hinder your progress with the language itself ...

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Also, executing from external flash is unusual for a Cortex-M0+

It don't run code from external flash, the external flash is like a disk, the code gets loaded to RAM.

 

The chip is cheaper to produce if it don't have flash on board (I bet that the boot code is placed in a metal mask same way as an org. 8051).

 

 

I remember about 15 years back when NXP LPC2138 was new, the code ran about 20% faster from RAM than flash.(and you could cycle count) 

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awneil wrote:

There are rumours abroad that ARM must have sunk some serious  cash into this - as a "fight-back" against the growth of RISC-V ...

The UART and SPI peripherals are ARM IP, so they may have supported the development by offering them license-free.  The Synopsys IP may have been free as well given ARM's relationship with Synopsys.

https://news.synopsys.com/2020-0...

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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But one thing could be if it's legal in US, if it don't have a unique serial number in the chip. 

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It don't run code from external flash, the external flash is like a disk, the code gets loaded to RAM.

Not entirely true - you choose whether you want to chew up your precious ram by loading code into it. The benefit is it will run very fast, or you use XIP (execute in place) and lean on the 16k cache to eek out some performance. If my experiences with the NXP IMXRT1062 are anything to go by, using XIP nobbles a 600MHz Cortex M7 to something like 70MHz. The effect probably wont be as bad with the 133MHz Cortex M0, but you have two of them to feed. With the IMX running from internal high speed ram, interrupt response is in the order of 15ns. 

 

 

Anyways, I ordered a couple of the Picos last night, so I should see then early next week. I'm not getting too excited as there doesn't seem to be PlatformIO support yet, but I expect that won't be too far away. My metric is if I can get a new board, plug it in, load up PlatformIO and have some code running in a couple of minutes, then I'm satisfied. If I need to screw around with settings etc, then I'm less impressed. The recent board I played around with is the Sipeed Longan Nano - took a little screwing around to get things happening. Arduino core support was not complete and there wasn't a prebuilt toolchain that worked on the Mac - I had to resort to using Windows.

 

As for RaspI designing the chip - I dare say they leaned on their bretheren at Broadcom to make it happen. Nevertheless, it would have cost over a million I expect to actually develop and get silicon. It might well be another Broadcom cast-off like the other RasPi cpus and they send the chips to China to get remarked with the RasPi logo.

 

 

 

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Kartman wrote:
(...) and they send the chips to China to get remarked with the RasPi logo.

 

ZOMG, even chip remarking is outsourced to China  😱

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Kartman wrote:
I ordered a couple of the Picos last night

I looked at one place, and they had a limit of one per customer!

 

As for RaspI designing the chip - I dare say they leaned on their bretheren at Broadcom to make it happen

Or ARM?  Not sure that Broadcom have anything to do with this one?

 

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Kartman wrote:
using XIP nobbles a 600MHz Cortex M7

 

Not surprised: even with QSPI you need a lot of bites to get those bytes: without looking at a spec sheet, you're probably looking at 4 or 6 bites to get the address in, another one for the control, and 8 for the data read. It improves by a factor of around two for sequential reads, so it's rather going to depend on the efficiency of the cache.

 

On a similar system we boot from QSPI flash solely to transfer the contents to RAM, with which the flash-less chip is plentifully supplied.

 

Neil

 

p.s. I looked into running from SPI for hardware controlled XIP for a 6502. Turned out to be possible but not practical... might have to look at QSPI or even OSPI for that.

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barnacle wrote:
does the clock have spread spectrum options? Because without that, it's going to have some difficulty meeting EMI regulations if you use this in a production part. Ask me how I know...
Spread-spectrum is one way of several (impedance)

EMC/ESD COURSE OUTLINE

...

 

Session 1.2 - Logic Devices and Circuit Boards

...

  • Spread Spectrum Approaches

...

 


High Frequency Measurements Site Index by Douglas C. Smith

 

"Dare to be naïve." - Buckminster Fuller

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barnacle wrote:

Not surprised: even with QSPI you need a lot of bites to get those bytes: without looking at a spec sheet, you're probably looking at 4 or 6 bites to get the address in, another one for the control, and 8 for the data read. It improves by a factor of around two for sequential reads, so it's rather going to depend on the efficiency of the cache.

 

On a similar system we boot from QSPI flash solely to transfer the contents to RAM, with which the flash-less chip is plentifully supplied.

 

Neil

 

p.s. I looked into running from SPI for hardware controlled XIP for a 6502. Turned out to be possible but not practical... might have to look at QSPI or even OSPI for that.

The RP2040 supports DDR, transfering 4 bits on every clock edge.  Winbond calls it DTR (double transfer rate).

https://www.winbond.com/resource...

 

So at 133Mhz, it can fill a 64-bit XIP cache line in 8 cycles.  Without the XIP cache, that would limit performance to 1 16-bit Thumb2 instruction every 2 clock cycles.

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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I can't think why (;-) but when I went to the YouTube app on one of my TVs tonight it started by recommending...
.
https://youtu.be/dUCgYXF01Do

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Thanks for the link, Cliff, that was both intriguing and alluring.

 

Perhaps I'll have to get the little Micro-Python book, the chip, and tinker a bit.

 

I wonder if the Sun will still come up over the horizon tomorrow if I do a project coded in something other than Basic!

 

JC 

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DocJC wrote:
I wonder if the Sun will still come up over the horizon tomorrow if I do a project coded in something other than Basic!

Is that the Beginner's All-purpose Sunrise Inducing Code ... ?

 

wink

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I wonder if using a Cortex M4 would greatly increase the MCU cost. A built in FPU would be nice.

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El Tangas wrote:
A built in FPU would be nice.

They are pushing their "highly optimised" software FP library...

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I wonder if the QSPI could connect to the big chip on Pi4 (A72) and then be used to load firmware and do communications for whatever the OS needed it to do. Maybe it will become a bridge to the 40 pin GPIO. I guess I am just trying to understand why they did this chip.

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"Dare to be naïve." - Buckminster Fuller

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You've still got the cost of entry - you need to send the cmd, address and dummy bytes before you get your read data - that's going to cost a few clocks. As Seymour Cray opined 'cache is no substitute for memory bandwidth'.

 

 

As for barnacle's suggestion of using serial flash for a 6502 - I would've thought the extra hardware alone would've made it impractical. One could use a little fpga and you'd get the 6502 for free.

 

 

 

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