On the thread https://www.avrfreaks.net/forum/quiz-fun-io-pin-and-4-levels we found out that, by adding two external resistors (pull-up and pull-down), an I/O pin (as of ATmega8) can output 4 voltages (by setting its DDR/PORT bits as 1/1, 1/0 0/1, 0/0 and 1/0).
Therefore, in theory, by combining the outputs of two such I/O pins, it is possible to get 16 different voltages (4*4).
Ideally, the 15 steps, from 0V to Vcc, are equal.
Any idea?... before I present mine 
Have fun,
Cheers,
Kerim
On the thread https://www.avrfreaks.net/forum/quiz-fun-io-pin-and-4-levels we found out that, by adding two external resistors (pull-up and pull-down), an I/O pin (as of ATmega8) can output 4 voltages (by setting its DDR/PORT bits as 1/1, 1/0, 0/0 and 1/0).
I think you mean 0/1 on that last one. Also note that the spec for the internal AVR pullup is miserable - anywhere from 20k to 100k. You might get even step voltages, but you don't know what they're going to be. S.
I think you mean 0/1 on that last one. Also note that the spec for the internal AVR pullup is miserable - anywhere from 20k to 100k. You might get even step voltages, but you don't know what they're going to be. S.
You are right about the actual internal pull-up and thank you for pointing out my mistake (0/1).
It is just a quiz for fun to those who like math... as I do
In this exercise, we suppose that the two internal pull-ups could be calibrated around a certain value and their temperature sensitivity is made to be relatively low.
In general, many topologies related to DAC cannot be practical if built by using discrete components. They are usually based on integrated circuits that are well calibrated (as in the various DAC ICs).
Hi
According to ATmega8's specifications, the I/O pin pull-up resistor's value is between 20 and 50 kΩ. It is slightly nonlinear. It varies with temperature and fabrication process, but one can expect the I/O pin pull-up resistors on a same chip to be quite similar.
Two I/O pins can generate 16 different voltage levels using 4 external resistors:
- R1 between the test point and the first I/O pin,
- R2 between the test point and the second I/O pin,
- R3 between the test point and VCC,
- R4 between the test point and GND.
The values of R1 and R2 must be different.
However:
- since the optimal external resistors' values depend on the internal pull-up resistors' values, which are unknown, the external resistors should be adjustable ;
- the difference between two voltage levels can be very weak. With optimistic -- but non optimal -- resistors' values and VCC=5V, the minimum voltage difference can be 100mV or less.
You mean this, right? Ignoring that R1/R2 and R3/R4 are swapped compared to your text description (I just modified an H resistor bridge pic from the net).
But solving those equations for the desired output voltages is not something I'm looking forward to...
Two I/O pins can generate 16 different voltage levels using 4 external resistors:
This may work. I will study it.
My solution is simply an update of what I did previously; in case of 1 pin and 4 levels.
I added two more resistors between the two pins. Their common node is the new output.
Assuming the internal pull-up resistance is 37K5 and R_hi on each pin is 120K (pin to Vcc), also R_lo on each pin is 56K (pin to ground), the optimum values of the added two resistors are close to 15K and 41K2 (39K+2K2). For these values, I got the table below:
| DDR1 | PORT1 | DDR2 | PORT2 | Outs(V) | Steps(V) | |
| 1 | 0 | 1 | 0 | 0 | 0.000 | |
| 1 | 0 | 0 | 0 | 1 | 0.327 | 0.327 |
| 1 | 0 | 0 | 1 | 2 | 0.730 | 0.403 |
| 0 | 0 | 1 | 0 | 3 | 0.909 | 0.179 |
| 1 | 0 | 1 | 1 | 4 | 1.323 | 0.414 |
| 0 | 0 | 0 | 0 | 5 | 1.591 | 0.268 |
| 0 | 1 | 1 | 0 | 6 | 2.027 | 0.436 |
| 0 | 0 | 0 | 1 | 7 | 2.229 | 0.202 |
| 0 | 1 | 0 | 0 | 8 | 2.773 | 0.544 |
| 0 | 0 | 1 | 1 | 9 | 3.052 | 0.279 |
| 0 | 1 | 0 | 1 | 10 | 3.311 | 0.259 |
| 1 | 1 | 1 | 0 | 11 | 3.677 | 0.366 |
| 0 | 1 | 1 | 1 | 12 | 3.966 | 0.289 |
| 1 | 1 | 0 | 0 | 13 | 4.299 | 0.333 |
| 1 | 1 | 0 | 1 | 14 | 4.628 | 0.329 |
| 1 | 1 | 1 | 1 | 15 | 5.000 | 0.372 |
I am afraid that the configuration, presented above (#4 and #5) that uses 4 resistors only, outputs levels far from the ideal ones; narrower range and, therefore, smaller steps.
Using two pins you can generate 65536 different levels.
Using two pins you can generate 65536 different levels.
You are right. And this could be done even by using one pin
What about speed?
As you know, there is a trade-off between resolution and speed in this case.
