Inspired by the recent discussion of video generation by AVR, I am knocking together a demo application. Basic theory is to run a counter at 64uS which triggers the line sync and output generator as an interrupt, and a match at 63uS which puts us to sleep beforehand to ensure a consitent delay between timeout and interrupt.
The polite way to do this:
// here at 63us sleepy_head: sei sleep reti // and here from sleep at 64us syncs: // do stuff reti
Which, after the syncs interrupt finishes, retis back to sleep_head which retis back to the main loop.
// here at 63us sleepy_head: sei sleep //reti // and here from sleep at 64us syncs: // do stuff pop iarg0 pop iarg0 reti
Now, instead of the double reti we lose the sync return address and the syncs' reti returns to the sleepy_head's return address. It takes just as long (4 cycles per reti, two cycles per pop) but somehow it feels a shade more elegant, given that the two interrupts are so closely coupled. Note that the sleepy_head routine is *complete*; there's no processing required there except to re-enable the interrupts.
Should I be run out of town on a rail, have my programmer's license revoked, pay a fine? I really can't decide... :shock: