question about HMATRIX connection on UC3B

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#1
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hi,

I'm thinking about optimizing my sensor data logging on SD card application code.

The sensor is connected to a USART, and it's data is read by DMA USART RX, and saved in buffer in SRAM, and the CPU takes SRAM data and send them to SD card connected on SPI.

So I'm thinking about the following setting:

void init_hmatrix(void)
{
	union
	{
		unsigned long                 scfg;
		avr32_hmatrix_scfg_t          SCFG;
	} u_avr32_hmatrix_scfg;

	// For the internal-flash HMATRIX slave, use last master as default.
	u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH];
	u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
	AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] = u_avr32_hmatrix_scfg.scfg;

	// it seems the following PBA slave setting does slows down microSD card logging.
	// For the PBA HMATRIX slave, use last master as default.
	u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_PBA];
	u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
	AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_PBA] = u_avr32_hmatrix_scfg.scfg;

	// it seems the following SRAM slave setting doesn't change microSD card logging speed.
	// For the SRAM HMATRIX slave, use last master as default.
	u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM];
	u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
	AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] = u_avr32_hmatrix_scfg.scfg;
}

in my case, the DMA master should only connects to SRAM slave, and CPU data master should only connects to PBA slave, so there should be no conflict, right?

but the test result shows that enabling PBA slave setting do slows down SD card writting speed a little, why?

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USART and SPI share the same PB(A) bus and are accessed through 2 masters, so the last default master might not be optimized.

-sma

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isn't the PDCA master read USART data from it's own bus, but not PBA bus?

and i also did a test with just sending data from SRAM to SD card on SPI, and I enabled the PBA slave last default master setting, and it also seems to get a little bit slower.

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PDCA has a dedicated handshaking channel for USART/SPI, but not for data, so data go through (32-bit) PBA bus. You should not set this optimization in your case.

-sma

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ok, then I know, thanks.

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Here's a followup question related to this: in this case where the PDCA transfers data from USART to SRAM, the PDCA is the master on the HSB, but who is the slave (SRAM or PBA)? It's not at all clear from the documentation but is critical for HMATRIX configuration in high bandwidth applications.