PWM...am I missing something?

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	TCCR1A |= (1<<WGM10);
	TCCR1B |= (1<<WGM13);
	OCR1A = 100;

	DDRB |=	(1<<PINB0) | (1<<PINB1);

PWM on PINB1(OC1A).

static inline void Start_PWM1(void){
	TCCR1A |= (1<<COM1A1);		/* set for non-inverted PWM */
	TCCR1B |= (1<<CS11); 		/* set Fpwm = xkHz */
	TURN_ON_LED1;	
}

When I start PWM, PINB1 goes high and stays high, it never changes when the counter hits top or bottom, in order to toggle the pin do I actually need enable OCIE1A and do a bit toggle? I thought setting the WGM bits to mode 9 was supposed to clear OC1A when upcounting and set OC1A when down counting....I have verified that it does change by running in debug mode through the ISP, by looking at PINB1 through a scope and measuring the voltage, its always high.

This is on an ATMega88P @ 20MHz, debugging platform is Dragon.

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Quote:

do I actually need enable OCIE1A

Table 15-2. Compare Output Mode, Fast PWM(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I'm sorry but I'm not making the connection from what you posted to what I'm supposed to do. Set COM1A1 should connect OC1A/OC1B, as you can see in my inline function Start_PWM1();, I set the COM bits accordingly followed by the clock. In the initial setup I set the WGM bits to mode 9 for Phase and Frequency Correct PWM, followed by setting PINB1(OC1A) as an output thus enabling PWM to function on that pin. I am not seeing what is missing to generate a wave form on OC1A....

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Quote:
I thought setting the WGM bits to mode 9 was supposed to clear OC1A when upcounting and set OC1A when down counting
No, in mode 9 OCR1A is TOP, and therefore sets the frequency, not the duty cycle. You can only use OCR1B as output in that mode.

Regards,
Steve A.

The Board helps those that help themselves.

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Quote:

Set COM1A1 should connect OC1A/OC1B, as you can see in my inline function Start_PWM1();,

I missed that.

Quote:

TCCR1A |= (1<<WGM10);
TCCR1B |= (1<<WGM13);

You are using ode 9 with OCR1A as TOP. You will not get any PWM on OC1A in that mode. You can, if you like, set up OCR1B and the COM bits and get PWM on OC1B in that mode.

(Think about it--what output >>PWM<< waveform did you expect when setting only one setpoint? You need period and duty for PWM.)

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I had though the duty cycle was set by OCR1A and frequency was controlled by the clock divider. Since PWM is an average of on and off, in which duty cycle is the pulse width, I was thinking that OCR1A setting how many counts it takes to toggle the output was controlling the duty cycle. Seemed perfectly logical to me.

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1 0
Clear OC1A/OC1B on Compare Match when upcounting.
Set OC1A/OC1B on Compare Match when
downcounting.

This is WGM = 9 according to the data sheet, how then are you supposed to control duty cycle if ORC1A is controlling frequency? If you can't control duty cycle and OC1A is always high or low how is that even PWM? I"m a little confused....

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If you use one of the 'fast pwm' modes (you get your choice of 8,9, or 10 bits), THEN you just store a number between 0 and 255 or whatever in the OCR1 to set the duty.

Imagecraft compiler user

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if I wanted to use phase correct PWM though, how would I set it up in order to have OCR1A as the duty cycle like in fast PWM? Can I use WGM 1,2,3 in the same way(since they are fixed TOP values thus freeing up OCR1A)?

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There are some contradicitons to what was posted here and what the tutorials say, take a look at the following:

Quote:
Mode of the timer is selected by setting WMGxx bits in TCCRx register. Bits for prescaler are CSxx. Note that timer is not running if prescaler is not configured. To run timer and start generating PWM wave you must set at least CS10 bit (Prescaler=1). To stop PWM, clear all CSxx bits.

The other very important register is OCRx, it controls duty cycle. For 16 bit timer1 it is 16 bit, for 8 bit timers it is 8 bit.

For modes where frequency is regulated, ICRx register controls frequency of the signal.

In Timer/Counter Control Register bits CSxx (Clock Select) controls frequency, bits WMGxx (Waveform Generation Mode) controls PWM mode.

That is straight from the AVR PWM tutorial and agrees with what I had originally though and posted above, my only mistake was setting it in WGM mode 9 where OCR1A defines top. CS controls frequency and OCR1A controls duty cycle in modes 1,2,3,5,6,7.

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Mode 8 is Phase and Frequency correct using ICR1 as TOP. With that mode both OCR1A and OCRC1B can be used for output. In mode 9, only OCR1B can be used as output.

Quote:
There are some contradicitons to what was posted here and what the tutorials say
I would not say that there are any contradictions, it is just that the tutorial is not very thorough about all the modes (which vary somewhat between timers anyways).

Regards,
Steve A.

The Board helps those that help themselves.

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Thanks for helping me clarify. I do have a question though, if mode 9 is used, since OCR1A is TOP which defines the period, what use is that mode of PWM if you cannot adjust duty cycle? There must be some mode of adjustment(even if fixed) or there is no purpose to doing it, one would simply turn on an output.

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Quote:

what use is that mode of PWM if you cannot adjust duty cycle?

There are TWO duty cycle registers and two PWM outputs for timer1 - A and B. If the A register is tied up being used to set the TOP (frequency) then it just means you are limited to one output and setting one duty - B

If you need two outputs then pick a mode where TOP is set in some other way (either a fixed value or ICR rather than OCR). You may want to ask yourself whether you really need Phase and Frequency Correct modes anyway?

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Ok, I now clearly understand the how PWM is done. I re-read very carefully figure 15-9 on the data sheet which explains the timing, compare matches etc. They clearly show an instance where a compare match happens at top and the output is not toggled, so if OCR1A is used at top then yes it will always just be high since there is no compare match point that is defined before top or bottom. I will probably use phase correct Mode 1 since I do not need to change frequency and DC motors typically are phase sensitive, thus also allowing me to change duty cycle on the fly since OCR1A is double buffered. Thanks again for the information, it always helps to get different perspectives, and I rather appreciate the input.

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Quote:

There are TWO duty cycle registers and two PWM outputs for timer1 - A and B. If the A register is tied up being used to set the TOP (frequency) then it just means you are limited to one output and setting one duty - B

If you need two outputs then pick a mode where TOP is set in some other way (either a fixed value or ICR rather than OCR).


Gee, I wish >>I<< would have thought to mention that. :roll:

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Quote:

Gee, I wish >>I<< would have thought to mention that

Clearly some folks just need something said multiple times before it finally sinks in?

BTW as OP has now mentioned "DC motors" I simply don't see the particular appeal of these Phase Correct modes. A motor doesn't care whether the variable width pulse is offset from 0 or not - in the realm of a DC motor where is "0" anwyay?