PWM Jitter added by ATMEGA328?

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I'm using the ATMEGA328 to make some PWM waveforms, which I'd like to ensure are as low in phase noise as possible. There doesn't seem to be a spec on phase accuracy of PWM outputs, relative to clock.

For example, using a crystal, I'm measuring around 1ns jitter on the clock output, as well as any derived PWM outputs. I assume this is from the crystal circuit.

I'm hoping that if I use a stand-alone oscillator, with specified jitter on the order of 1ps (easily available), the resulting PWM output jitter will be not-too-much higher. Make sense? Obviously I'll try it, but it's tricky to measure, and was hoping there was a spec (or experience) somewhere.

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I'm a bit confused. How can you expect nanosecond accuracy from a piece of clocked logic that is running, at best, at 20MHz so has a 50ns clock period?

(but hey, what do I know, I'm just a software engineer ;-))

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Quote:

...but it's tricky to measure,...

Indeed--how are you measuring the clock in the first place? And your measuring instrument must have some GHz of bandwidth to resolve this 1ns of jitter?

Given the whole of your post, I'd guess you are well aware of these things. Now, tell a bit more about the PWM -- frequency and bits and typical duty cycle. Does the clock jitter "catch up" over a number of clock cycles? Then, depending on how many clocks there are in a PWM period there might not be much effect?

Also, as a curiosity, what is this precision PWM driving?

Kind of an interesting question. I wonder what the results are if one does the same observations on e.g. an Xmega or different flavours of CortexM. And with and without PLL-derived master clock. And (for those that know them) on programmable logic like FPGA.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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A PWM that does not use interrupts should be only slightly worse than the source clock, jitter-wise.

This is because its all generated by hard logic. There is nothing sequential determining where the edges are. So, think of a clock, a counter, and an N-bit comparator in hardware. The counter is certainly synchronous. I'll bet the comparator is, also.

Jitter might be a bit worse if you don't let the counter overflow at its natural count (that is, set the period according some register value). But, this should be no worse than the jitter on the PWM edge that is also controlled by a register compare.

There won't be any spec because this is outside the norm of MCU applications. You should, however, be able to rely on what you find by testing one device.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Thanks very much.

To answer the above, I don't need ns *resolution*, but I do need the consistency and lack of phase error for the resolution I do have.

I am measuring with a 2GHz SR (200MHz) scope, and while it's tough to see jitter in detail, it's definitely noticeably higher with a crystal/atmega than with a dedicated oscillator (I happen to have one on a different project).

The PWM's are indeed made using the usual counter logic without interrupts or overflow. I'm hopeful this circuitry doesn't impose much jitter.

The application is for a PWM digital amplifier (basically class D) for low frequency RF signals (hundreds of kHz), fwiw.

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Quote:

PWM digital amplifier ... (hundreds of kHz),

Is an AVR8 really the right hammer for this nail? Especially a '328 without a "fast" PWM clock?

20MHz AVR clock; say 200kHz PWM period gives 100 counts per period-- 6-7 bits. Not much resolution.

But I'm not that familiar with that app area.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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That's all the resolution I need. The fine structure of the pulse widths are varied elsewhere.

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jrs454 wrote:
I am measuring with a 2GHz SR (200MHz) scope, and while it's tough to see jitter in detail, it's definitely noticeably higher with a crystal/atmega than with a dedicated oscillator (I happen to have one on a different project).
Nevertheless, you're measuring at the limits of your scope. A 1 ns time with a scope sample time of 0.5 ns. Keep in mind that although it is a 2 GHz sample rate, the bandwidth is still 200 MHz. At 200 MHz, input signal attenuation is 3 dB. What is it at 2 GHz?

I wouldn't be too confident with a conclusion of 1 ns jitter without confirming with another instrument.

That said, you can use the CKOUT fuse to measure the clock signal direction without disturbing the oscillator the way you might by measuring from XTAL1.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Yes, you're correct of course. But I was able to distinguish the difference in jitter from a regular crystal driving the ATMEGA, vs. a standalone low-jitter oscillator (which is well specified - and well below scope resolution). My spectrum analyzer will probably do a better job.

I was measuring jitter on my CKOUT as well as my PWM waveforms. I would imagine that the presence of the probe on the crystal circuit could alter things a bit.

I just wish this was something specified; if I know jitter going in, I'd like to know jitter coming out.

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You have a unique app (at least IME).

For even my "precision" PWM apps, I don't think sub-cycle-time jitter would matter. E.g., an example of my app might be a pneumatic pressure controller using 9-bit PWM. It is closed-loop, working with commanded setpoint and pressure feedback using AVR8 10-bit A/D values.

Now, those values only have 1000 counts--and generally aren't perfect anyway.

The 9-bit PWM output runs with a /8 prescaler, so 1us per count with ~8MHz clock.

At half-scale of say 256 counts, that is 256us of on-time. 100ns one way or the other is not material for the described app. And there are a couple thousand clocks in that time; the jitter might well not be present during the critical clock.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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jrs454 wrote:
I was measuring jitter on my CKOUT as well as my PWM waveforms. I would imagine that the presence of the probe on the crystal circuit could alter things a bit.
A probe on CKOUT will have no effect on the crystal circuit. If you have your probe on XTAL1, it will have a measurable impact. If you have it on XTAL2, it will likely prevent oscillation.

Which oscillator mode are you using?
Have you tried full swing?
What value capacitors are you using?
Is this on a breadboard? PCB?
Have you characterised (or simulated) the parasitic capacitance of traces connecting the crystal and caps to the AVR?
Does the total capacitance (caps + parasitic + pin) meet the AVR's and the crystal's specifications? Do they match?
What is the Q factor of the crystal you are using? The stability of the crystal is more likley to affect clock jitter than the components internal to the AVR.

If you're looking for sub-nanosecond jitter, you're going to have to do more than just plunk a crystal down next to the mcu.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Quote:

I just wish this was something specified; if I know jitter going in, I'd like to know jitter coming out.

LOL, you might want to look at this thread that I found with a Google search. You mentioned "class D amplifier"...
https://www.avrfreaks.net/index.p...

Quote:
Some of us go out of our way to make the clock jitter for lower EMI.

Quote:
I've noticed a few Class-D amplifier chips doing the spread-spectrum trick to get EMI clearance, ...

That was with the internal oscillator. (And apparently from the thread, jitter there is well-known.)

I've lost track in this thread. ;) CRS and all that...

Mega328 is the target. What are the clock fuses? Do you get the same result with full-swing as well as econo-mode? Is this a "sample defect"? -- do all boards show the same characteristics? Tried more than one crystal? Adjusted cap values? Matched the caps? Tried a trim cap? Squeaky-clean crystal layout, right next to the pins, with a ground guard plane?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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joeymorin wrote:
jrs454 wrote:
I was measuring jitter on my CKOUT as well as my PWM waveforms. I would imagine that the presence of the probe on the crystal circuit could alter things a bit.
A probe on CKOUT will have no effect on the crystal circuit. If you have your probe on XTAL1, it will have a measurable impact. If you have it on XTAL2, it will likely prevent oscillation.

Yes of course, I was measuring only on CKOUT, sorry if I was not clear.

Quote:

Which oscillator mode are you using?
Have you tried full swing?
What value capacitors are you using?
Is this on a breadboard? PCB?
Have you characterised (or simulated) the parasitic capacitance of traces connecting the crystal and caps to the AVR?
Does the total capacitance (caps + parasitic + pin) meet the AVR's and the crystal's specifications? Do they match?
What is the Q factor of the crystal you are using? The stability of the crystal is more likley to affect clock jitter than the components internal to the AVR.

If you're looking for sub-nanosecond jitter, you're going to have to do more than just plunk a crystal down next to the mcu.

Using full-swing, with a clean PCB layout, and 22pF on each crystal leg, all within specs. I would consider jitter to be very low right now by most standards; I just want it lower!

But sure, if I need to do more than plunk a crystal down, that's fine. I can use a standalone oscillator (and hey, saves me an IO pin!)

My question is, will this be enough: if I had a "perfect" clock coming into the ATMEGA, how much jitter would the ATMEGA add to the PWM waveforms?

Clearly from the other forum post this isn't something at all specified by Atmel; I suppose few have explored this. If I can measure it accurately (jitter in vs jitter out) I'll do so and shed some light on this territory.

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Got a part number (or datasheet) for the crystal you're using?

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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http://www.txccrystal.com/images... ~12Mhz

I can believe this is 1ns jitter or so.

But again, I really don't need to rely on a crystal. I am happy to use a standalone oscillator - as long as the ATMEGA doesn't impose too much jitter.

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jrs454 wrote:
I can believe this is 1ns jitter or so.
No mention of Q factor, so no way to guess how much jitter is the crystal's fault. Further, unless your caps are perfectly matched to the parasitic capacitance of the PCB traces, package pins, and the demands of the crystal and those of the AVR's inverting oscillator, you won't achieve anything near the crystal's optimal stability.

Quote:
But again, I really don't need to rely on a crystal. I am happy to use a standalone oscillator - as long as the ATMEGA doesn't impose too much jitter.
As it isn't specified or characterised, you'll have to do your own tests. However I expect the jitter imposed by the internal PWM logic would be negligible.

There is a down-side to oscillators with high Q factors: they are much more sensitive to disturbances (electrical, temperature, mechanical), and they take longer to stabilise after start-up.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Thanks. From my understanding jitter has as much to do with the crystal drive circuit as much as the crystal itself, and the ATMEGA internals are unknown, so it's hard to predict. [ I'm not too worried about slow freq drift, fwiw. ]

I am encouraged by your opinion that added jitter to PWM from a clean clock would be negligible. I will have to test it, of course. But that's two votes from those more experienced than I...

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jrs454 wrote:
From my understanding jitter has as much to do with the crystal drive circuit as much as the crystal itself
It's certainly a factor, and as you say the AVR internals aren't known, but I'm not prepared to say that they'll have as great an effect on jitter as the crystal or its caps.

With a high-Q crystal (and properly matched caps), oscillation is simply not possible outside a very narrow range of frequencies centred at the crystal's rated frequency. This is the crystal's bandwidth. A high-Q (low bandwidth) crystal translates to a lower jitter.

Were a crystal with sufficiently high Q mated to an inverting amplifier which contributed too much jitter on its own, it just wouldn't sing.

An example of a high-Q crystal is a low-frequency watch crystal. The AVR inverting amplifier can be configured to happily use one of these crystals to create a very stable oscillator. While the internals of the AVR's inverting amplifier are unknown, and indeed there may be separate amplifiers used for the different oscillator modes, I see no reason to conclude that the AVR is at fault here.

You seem already to have decided to go with an external oscillator, and that may be just as well for your application. However if you're interested in characterising the inherent jitter of the AVR's clock amplifier, you'll need to get your hands on a high Q crystal with a detailed datasheet and a good capacitance probe to select the appropriate caps for your crystal/avr/pcb combination.

Although it's geared towards the selection and testing of low-frequency crystals, have a look at AVR4100 for some idea of what makes a crystal oscillator tick.

Quote:
I am encouraged by your opinion that added jitter to PWM from a clean clock would be negligible. I will have to test it, of course. But that's two votes from those more experienced than I...
Don't place too much faith in my ramblings. I haven't done any bench tests on this topic to support opinion with fact ;)

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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jrs454 wrote:
I just wish this was something specified; if I know jitter going in, I'd like to know jitter coming out.
Jitter sensitive applications aren't really the target of microcontroller internal logic. I can't think of any microcontroller vendors that specify jitter (or even propagation delay).

- S

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For sub ns jitter, were in the analog realm. One would think noise on the power supply would contribute as would dynamic loading of port pins via the power rails. I think you'd want to ask chip designers questions as to what might contribute to instantaneous jitter.

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Supply noise and such can certainly have an effect.

I did the measurements, and found that with a standalone oscillator, jitter going out of the ATMEGA is essentially identical to what's going in, to the resolution of my 200MHz scope. My uncertainty is about 0.5ns, but there was no observed increase.

With a crystal, I was about 1ns, clearly higher.

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I would be interested to see what your SA has to say in each case...

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Got a nice clean peak from my SA (HP 3585A); with a very long sweep, it was -90dB down roughly 40Hz each side of my 400kHz square wave fundamental.

This would imply at worst what, 100ps or so?

I'm pretty sure this is just limited by the resolution of the equipment.

[ Oscillator is rated to 1ps ]

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jrs454 wrote:
Got a nice clean peak from my SA (HP 3585A); with a very long sweep, it was -90dB down roughly 40Hz each side of my 400kHz square wave fundamental.
That's what, a 40 MHz SA? What does it have to say about the oscillator itself?

Quote:
This would imply at worst what, 100ps or so?
I make it +/- 250 ps (at 90 dB), but hard to say how much of that is a limitation of the SA.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Same result with the oscillator (obviously in a different frequency range). It's definitely the limit of the equipment; the -90dB is the noise floor. Any distortion is within the envelope of the main peak.

I will probably need different gear to measure more precisely. (I'm not sure if that will be necessary.)