PWM Duty Cycle - Available Duty Cycles

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As part of trying to learn about AVR MCUs, I have been trying to understand how to use hardware PWM. In researching materials on duty cycle, I came across this AVR Freaks thread. I am trying to see if I understand the import of this thread correctly. I tried various searches on this forum and Google, and found some stuff. I have also read the datasheet for the ATmega8 (the device that I currently have access to).

Based on what I read, I think that the duty cycles should work out as described below. Am I understanding this correctly?

If I use timer1 in Fast PWM mode (Mode 14, TOP = IRC1), and set top to 0x03 (the minimum resolution), then TCNT1 and OCRA1 have the following possible values:

  • 00
  • 01
  • 10
  • 11
According to the ATMega8 datasheet, if non-inverting Fast PWM mode, the counter counts from BOTTOM (0x00) to TOP (in my example 0x03) then restarts at BOTTOM. So, TCNT1 will count according to the following sequence:

00 -> 01 -> 10 -> 11 -> 00

For inverted Fast PWM mode, OCA1 is set at BOTTOM and cleared on Compare Match. Therefore, the duty cycles are as follows:

  • If OCRA1 is set to 0x00, the OC1A pin is cleared at BOTTOM and continues LOW for the entire 00 -> 01 -> 10 -> 11 -> 00 sequence (i.e. High for 0 counts, LOW for 4 counts equals 0% duty cycle)
  • If OCRA1 is set to 0x01, the OC1A pin is set at BOTTOM and continues HIGH until TCNT1 reaches 0x01 at which time OCA1 clears and remains cleared for the 01 -> 10 -> 11 -> 00 sequence (i.e. High for 1 counts, LOW for 3 counts equals 25% duty cycle)
  • If OCRA1 is set to 0x02, the OC1A pin is set at BOTTOM and continues HIGH until TCNT1 reaches 0x02 at which time OCA1 clears and remains cleared for the 10 -> 11 -> 00 sequence (i.e. High for 2 counts, LOW for 2 counts equals 50% duty cycle)
  • If OCRA1 is set to 0x03, the OC1A pin is set at BOTTOM and continues HIGH until TCNT1 reaches 0x03 at which time OCA1 clears and remains cleared for the 11 -> 00 sequence (i.e. High for 3 counts, LOW for 1 counts equals 75% duty cycle)
  • Cannot have 100% duty cycle since OCRA1 only has 4 "states," and all have been used

For inverted Fast PWM mode, OCA1 is set on Compare Match and cleared at Bottom. Therefore, the duty cycles are as follows:

  • If OCRA1 is set to 0x00, the OC1A pin is set at OCRA1 which is also equal to BOTTOM and continues High for the entire 00 -> 01 -> 10 -> 11 -> 00 sequence (i.e. High for 4 counts, LOW for 0 counts equals 100% duty cycle)
  • If OCRA1 is set to 0x01, the OC1A pin is cleared at BOTTOM and continues LOW until TCNT1 reaches 0x01 at which time OCA1 sets and remains set for the 01 -> 10 -> 11 -> 00 sequence (i.e. LOW for 1 count, HIGH for 3 counts equals 75% duty cycle)
  • If OCRA1 is set to 0x02, the OC1A pin is cleared at BOTTOM and continues LOW until TCNT1 reaches 0x02 at which time OCA1 sets and remains set for the 10 -> 11 -> 00 sequence (i.e. LOW for 2 counts, HIGH for 2 counts equals 50% duty cycle)
  • If OCRA1 is set to 0x03, the OC1A pin is cleared at BOTTOM and continues LOW until TCNT1 reaches 0x03 at which time OCA1 sets and remains set for the 11 -> 00 sequence (i.e. LOW for 3 counts, HIGH for 1 counts equals 75% duty cycle)
  • Cannot have 0% since OCRA1 only has 4 "states," and all have been used

In contrast, in the case of Phase Correct PWM, the counter counts from BOTTOM to TOP and then from TOP to BOTTOM (with the counter being at TOP for one timer count). In the non-inverting Phase Correct mode, OCA1 is cleared on Compare Match when counting up and set on Compare Match when counting down. In Phase Correct mode with 2-bit resolution (TOP set at 0x03), TCNT1 has the following possible values:

  • 00
  • 01
  • 10
  • 11
  • 10
  • 01
So, TCNT1 will count according to the following sequence:

00 -> 01 -> 10 -> 11 -> 10 -> 10 -> 00

Therefore, the duty cycles are as follows:

  • If OCRA1 is set to 0x00, the OC1A pin is cleared at BOTTOM and continues LOW for the entire 00 -> 01 -> 10 -> 11 -> 10 -> 10 -> 00 sequence (i.e. High for 0 counts, LOW for 6 counts equals 0% duty cycle)
  • If OCRA1 is set to 0x01, the OC1A pin is set at BOTTOM and continues HIGH until TCNT1 reaches 0x01 at which time OCA1 clears and remains cleared for the 01 -> 10 -> 11 -> 10 -> 10 at which point OCA1 sets for the 10 -> 00 sequence (i.e. High for 2 counts, LOW for 4 counts equals 33% duty cycle)
  • If OCRA1 is set to 0x02, the OC1A pin is set HIGH at BOTTOM and continues HIGH until TCNT1 reaches 0x02 at which time OCA1 clears and remains cleared for the 10 -> 11 -> 10 sequence at which point OCA1 sets for the 10 -> 01 -> 00 sequence (i.e. High for 4 counts, LOW for 2 counts equals 66% duty cycle)
  • If OCRA1 is set to 0x03, the OC1A pin is set at BOTTOM and continues HIGH until TCNT1 reaches 0x03 at which time OCA1 "clears and re-sets" and remains set for the 11 -> 10 -> 01 -> 00 sequence (i.e. High for 6 counts, LOW for 0 counts equals 100% duty cycle)
  • Cannot have 100% duty cycle since OCRA1 only has 4 "states," and all have been used

For inverting Phase Correct mode, OCA1 is set on Compare Match when counting up and cleared on Compare Match when counting down. So, duty cycles should be same as for non-inverted mode, but reversed order:

  • 100% duty cycle for OCRA1 = 0x00
  • 66% duty cycle for OCRA1 = 0x01
  • 33% duty cycle for OCRA1 = 0x02
  • 0% duty cycle for OCRA1 = 0x03
I think that Phase and Frequency Correct mode should work the same as Phase Correct (as for as duty cycle discussion above goes).

Am I interpreting and understanding this correctly?

Russ

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I thought that setting OCR to 0 would give 0% and setting OCR to TOP would give 100% so that the entire range from 0% to 100% (but in binary steps) is achievable?

I guess the easy answer is to check this in the simulator - while it cannot be trusted to do PWM on 16 bit timers (maybe Sim2 can?) you should be able to check accurate operation using an 8 bit timer. Just set it to TOP=0xFF and see what happens to OC0 output for OCR=0 and OCR=0xFF

Even if 0x00 or 0xFF does not achieve 0%/100% then it doesn't matter so much because your 2 bit example is very granular, with 8 or more bits then perhaps you only get to achieve 255/256% at the top end but that's near as dammit to 100%. Certainly for things like LED brightness or servo movement the 1/256% is pretty immaterial. In a 16 bit mode (TOP=0xFFFF) on a 16 bit timer the "unachievable step" would be even smaller (by a factor of 256)

Last Edited: Sun. Jan 10, 2010 - 08:58 PM
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Quote:

I thought that setting OCR to 0 would give 0% and setting OCR to TOP would give 100% so that the entire range from 0% to 100% (but in binary steps) is achievable?


In general, no. See the recent thread on this...
https://www.avrfreaks.net/index.p...
Also
https://www.avrfreaks.net/index.p...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:
See the recent thread on this...
https://www.avrfreaks.net/index.p...
Also
https://www.avrfreaks.net/index.p...

The first thread you linked is the one that got me thinking about this...Is my understanding of how duty cycle would be calculated (as set forth above) generally correct?

I know that 2-bit resolution is an extreme example, but I was curious that I was understanding the analysis correctly.

Thanks.

Russ