I found an odd thing today.
We have projects using ATxmega256A3U with 16MHz oscillators, by which we run the chip at 32MHz using PLL. The oscillator was configured as follows:
OSC.XOSCCTRL = 0xCBU; /* 16-20MHz, 16K clock startup time */ OSC.CTRL = 0x09U; /* External osc. starts (+ internal 2MHz keeps running) */ while ((OSC.STATUS & 0x08U) == 0U); /* Wait for osc. */ OSC.PLLCTRL = 0xE4U; /* PLL: External osc. x4 /2 */ OSC.CTRL = 0x19U; /* PLL starts (+ ext. osc., int. osc. keep running) */ while ((OSC.STATUS & 0x10U) == 0U); /* Wait for osc. */ CPU_CCP = 0xD8U; CLK.CTRL = 0x04U; /* Run on PLL */ OSC.CTRL = 0x18U; /* Internal osc. stops */
This on the ATxmega256A3U produces the expected result: the chip is running at 32MHz. However now that we picked up some ATxmega128A1U's for the larger pin count (which some of our projects required, being more convenient than using for example an SPI I/O extender), the same code seems to fail, resulting in the chip running at 64MHz (XMegas would usually run at this frequency just fine, the problem becomes apparent with stuff clocked by the main clock, such as UART baud rates).
Changing the line configuring the PLL fixes the problem:
OSC.PLLCTRL = 0xC2U; /* PLL: External osc. x2 */
Which makes it appear like the PLLDIV configuration flag had no effect on the ATxmega128A1U. The errata doesn't seem to carry anything relevant over this.
Could this be? Or is there something I am overlooking here? It doesn't seem like that these two chips had differences in their oscillator controls.