PLL clock, changing values in U-Boot

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#1
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(I think this message belongs here since it's about avr32 hardware)

I'm trying to change PLL frequency in AP7000 (ngw100) without re-flashing U-Boot.
I did this:

setenv new_speed 'mw.l 0xfff00004 0x80808000; mw.l 0xfff00020 0x10050011'

I'm clocking the PLL from a 24.576MHz. I want to get a 147.46MHz main clock and the PB dividers as they are on the values above.

I know that I should wait for the PLL to lock..or maybe turn it off first?

The problem is that sometimes the board runs alright and the ABDAC does fine at both 48kHz and 96kHz, but some other times things don't go right and the abdac output sounds as if frequency is oscillating around some unknown value.
I know u-boot does a different thing when setting the PM settings, but if the problem is on what I'm doing, is there another option rather than burning u-boot again?

EDIT: maybe there is a problem with PLL count in PLL control.

Thanks

carlos

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I finally got it working by recompiling U-Boot with the right modifications and reburning it to the flash.
As HCE said on the irc channel, it's important to wait for the lock bit in order to assure proper PLL operation.