AVR Freaks

Using a mega48/88/168 as an example:
Set the bits of the appropriate PCMSKx register high to enable pin change detection on that pin. For PD2 (PCINT18) that would be:

Then enable the interrupt for the corresponding vector and of course the global interrupt flag:

The provide the ISR for that vector that does what you need. For avr-gcc this would look like this:

For one pin (or more generally, one pin per PCINT vector), that is all you really need. If you have more that one pin per vector enabled, then as Levenkay says, you have to have code in the ISR that determines which of the pins caused the change. This can be done by keeping a variable that stores the value of the register the last time the ISR was run and comparing to the current value. There can be problems with timing issues, however, since by the time you get to the ISR, another pin may have changed (or even worse, the one that did change changed back). These can be difficult to deal with, but how serious a problem it is depends on the characteristics of your application.

becomes

becomes:

For the ISR first fill in the PCINT2 vector down near 0:

@clawson
Yes at this low level the C and ASM are very similar.

I can't do the fast timer trick because I have too much else to do as well and that would tie up the processor most of the time for no result.

However I've had a think and the "fast pulse" is not a problem, that will be a glitch which will be ignored.

As for the speed, I'm bit banging the Rx and Tx of two asynch serial lines at the same time at up to 20kHz but most likely 9600 or even 4800. The two signals however are totally independant and therefore edges could arrive at any time.

I think I've got it pretty much sorted (as a design, no coding yet) but Koshchi's comment got me wondering about the situation when two edges arrive seperated by a very short period, say < the time to service the interrupt and read the port, eg

I think this works.

Sorry for the confusion, I do need a timer for generating the bits and for testing the level at the 50% mark when receiving them, I'm only talking about detecting the incoming bit edges here.

Hi Sparrow2,

I appreciate your time but I think I've exceeded my ability to explain what I want to do with words.

Attached is a block diagram, there are two data streams NRX->ARX and ATX->NTX.

ATX->NTX is async chars but the chip doesn't care, it basically just transfers the ATX pin levels through to NTX but does apply some tests on the data like "has it been LOW for too long?"

NRX->ARX has to assemble the chars received on the NRX pin and buffer them for later transmission on the ARX pin.

I can flow control the ATX data stream by dropping CTS/ERR but have no control over the incoming data on NRX.

And just to make it more interesting I have to bit rate detect both data streams as they could be anything within a range as yet to be determined and different to each other. I also have to detect bus clashes on the NTX/NTX pair (these go to a line transceiver).

Anyway this is probably getting too much for a thread here and I don't expect you to spend hours diagnosing my design.

I do however like the idea of running a fast timer interrupt and will look into that.

As to whether I can keep up with constant data, for the time being that is in the lap of the Gods.

Rob

Thanks sparrow, I'd forgotten about manchester, that would solve the clock recovery problem. As for the 485 look alike I'm using whatever transcievers make sense so they will handle the actual line levels.

Anyway I've obviously still got a lot of design work to do, good thing that's the fun part.