Phase correct pwm OCR vs Fast PWM OCR

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Hello all. Well I had a question while reading about phase correct pwm and fast pwm, why in the fast pwm the OC0 pin switches from low to high at OCR0+1, as it is written in the datasheet or in mazidi's book that when it reaches the OCR0 value the flag is set on the next clock because it compares at a clock tick and then sets on the next clock tick, which is understandable, however upon reading the phase correct pwm it is written that the OC0 pin would toggle in the same clock time with comparing, how is that? shouldn't they both have same behavior in regards to comparing and setting? 

Sherif Nassar

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sherifb96 wrote:
how is that? shouldn't they both have same behavior in regards to comparing and setting? 

Why does it mater to you, it is what it is, the designers of the chip do not need to explain to us why they did what they did, just what they did, so we can use it in our projects.

Jim

 

 

(Possum Lodge oath) Quando omni flunkus, moritati.

"I thought growing old would take longer"

 

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well if it is the way the chip is designed then that would be the answer to my question indeed, I was asking because i thought it is me that is not understanding how it works or something, because in normal mode timers the overflow flag is set also after it reaches the top by a tick, same goes to ctc the ocr flag is set after it reaches ocr0 by a tick, so i thought the comparison has to go this way hardware wise, so i couldnt understand when i found  the phase correct comparing and setting in same tick. however if it is the way the avr is designed then thank you.

Sherif Nassar

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sherifb96 wrote:
from low to high at OCR0+1
If you are asking "why the +1?". It's because if you want 250 steps (say) you actually set OCR to 249 because the counting sequence INCLUDES 0. On a smaller scale if you wanted 4 steps you would set OCR to 3 then the sequence would be 0, 1, 2, 3,   0, 1, 2, 3,   0, 1, 2... As you can see that gives you the 4 steps you want in a single cycle.

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Each ramp in Fast PWM gets its own TOP and BOTTOM count, so two ramps hit TOP and BOTTOM twice. In Phase Correct PWM, the TOP and BOTTOM count only occur once for each Up/Down pair. So the two missing counts per pair gives you a difference of +1 count per ramp between modes.