Phase correct PWM mode 11 clarifications

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Hi everyone,
as I promised a few posts ago, I still need your help. I'm completing the study of timers and PWM wave generation. In particular, I am approaching the understanding of phase correct PWM. It is quite clear to me for this type of PWM as the value of the TOP is fixed. But I really can't understand mode 11 in Table 16-5.Waveform Generation mode reported in the datasheet (Atmega164A...). Since the TOP is set by OCR1A, it is not possible to change the state on the OC1A pin.
Please give me clarification and maybe an example code that makes the way of working even more understandable.
Thank you so much.

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There’s a zillion tutorials on the AVR timers. They've been around for nearly 20 years and not much has changed. To aid your learning, I’d suggest you seek these out.

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Dear Kartman,
thank you for your intervention. In addition to studying the AVR documentation, I also searched for tutorials. But I can't find anything about the specific phase correct PWM mode. Specifically, mode 11 where TOP = OCRnA.
I will try to look better, but if for the other timers everything seems clear enough for this specific case I am really confused. I will try found the tutorial that you have told me.

As always, I thank you for your prompt participation.

Thanks a lot!

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codabat wrote:
Since the TOP is set by OCR1A, it is not possible to change the state on the OC1A pin.

 

From my understanding of table 16-4, on mode 11, if you set COM1A1/A0 to 01 (i.e., toggle OC1A on compare match), you can still use the OC1A pin to generate a square wave, so it doesn't become totally useless.

 

But remember you can use the capture register as top if you need both PWM outputs. BTW, some time ago I wrote a code snippet on phase correct PWM, it can be used to drive complementary mosfets with "dead time" (if you use sensible values, of course, otherwise white smoke is a strong possibility...)

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In the modes where OCR1A sets TOP (ie the PWM frequency) then channel A is not active so you can only use channel B (ie OCR1B/)C1B) for the actual output. This is true of all modes where OCR1A sets top: 4, 9 , 11, 15, not just the phase correct PWM one.

 

If you want to use A as well then pick a mode where frequency is fixed (or set by ICR instead). (that is Mode 10 rather than Mode 11).

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Hello Clawson,
Thanks for your comments. I think I guessed what you're telling me. However, I reflect a bit between what you told me and from what I'm reading from the datasheet.
As soon as, I believe, to have just a little clearer idea, I would like to know your thoughts and understand if I am wrong or on the right path.
Thanks a lot for now. See you tomorrow.

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Hello El Tangas,
Thanks for your comments. I think I guessed what you're telling me. However, I reflect a bit between what you told me and from what I'm reading from the datasheet.
As soon as, I believe, to have just a little clearer idea, I would like to know your thoughts and understand if I am wrong or on the right path.
Thanks a lot for now. See you tomorrow.

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codabat wrote:
As soon as, I believe, to have just a little clearer idea, I would like to know your thoughts and understand if I am wrong or on the right path.
I have no idea what you are talking about so am unable to answer. It is a purely a statement of unequivocal fact that when A is being used to set frequency it cannot be used to set duty - so the channel controlled by A is unusable as an output in this case.

Last Edited: Tue. Sep 17, 2019 - 09:17 AM
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clawson wrote:
In the modes where OCR1A sets TOP (ie the PWM frequency) then channel A is not active so you can only use channel B (ie OCR1B/)C1B) for the actual output.

 

Hi Clawson,
Before explaining how much I was able to understand, I would like to express my gratitude and that what is written to me, especially from people so kind and willing to devote their time and above all infinitely wiser than me for me all this is worth gold. When I approach things I don't know, but I dream of learning, I try to do it in the most Socratic way: "I know that I know nothing"!

In your last post you wrote to me:

"I have no idea what you are talking about so I can answer. It is a statement of unequivocal fact that it is being used to set frequency it cannot be used to set duty - I know the channel controlled by an output in this case. "

I agree that it is a pure affirmation and that it expresses a fact. However, to a person with little experience, as in my case, it sounds like an unfinished concept or that leaves something unsaid to be implied. The first thing that comes to mind is: what utility can this mechanism have? Are we saying, sorry if I say something wrong, that in this way I generate a continuous signal of 5V if in non-inverted mode or 0V if in inverted-mode? In this regard, I am also reminded of your statement:

"In the modes where OCR1A sets TOP (ie the PWM frequency) then channel A is not active so you can only use channel B (ie OCR1B /) C1B) for the actual output."

However, I don't understand it and don't understand how it is related and how it could be implemented.

Nevertheless, I say this with the humility of a person who still has much to learn, reading the datasheet it would seem not entirely right your statement. If within the Phase Correct PWM, we observe the Compare Output mode, we can see that with COM0A1 = 1, and COM0A0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. Therefore there must be signal switching and therefore the formation of a duty cycle.

I wonder, therefore, if your statement, but also what is written in the datasheet does not mean that the mode 11 of the Waveform and all the configurations in which TOP = OCR1A (top on fixed) switching does not happen anymore at a pure hardware level but should I use interrupt support (software)? In particular, in mode 11 the compare event  (TOP) may be the moment in which we can vary the value of the OCR1A and therefore generate a PWM with variable duty cycle.

To verify this, I wrote this little code that would seem to confirm this interpretation:

 

/*
 * PhaseCorrectPwmMode.c
 *
 * Created: 15/09/2019 12:14:17
 * Author : codabat
 */ 

#include <avr/io.h>
#include <avr/interrupt.h>
#ifndef F_CPU
#define F_CPU 16000000L
#endif

int v[4] = {17476,17476,34952,34952};
volatile int counter = 0;
void init_timer_phase_correct_pwm(void);

int main(void)
{
    init_timer_phase_correct_pwm();
    while (1) 
    {
    }
}

void init_timer_phase_correct_pwm(){
    cli();
    DDRD |= (1 << PD5); //PIN OC1A

    TCNT1 = 0;
    TCCR1A |= (1 << COM1A1) | (0 << COM1A0) | (1 << WGM11) | (1 << WGM10);
    TCCR1B |= (1 << WGM13) | (0 << WGM12) | (1 << CS12);
    OCR1A = v[counter]; 
    TIMSK1 |= (1 << OCIE1A);
    sei();
}

ISR(TIMER1_COMPA_vect){
    
    counter++;
    if(counter<4){
        OCR1A = v[counter];
    }else{
        counter = 0;
        OCR1A = v[counter];
    }
}

 

The following is the wave detected with the oscilloscope:

 

 

While I try to create a Correct Phase PWM with the TIMER0 and therefore with the fixed 8bit TOP, it is enough that I write the following code:

 

/*
 * PhaseCorrectPwmMode.c
 *
 * Created: 15/09/2019 12:14:17
 * Author : codabat
 */ 

#include <avr/io.h>
#include <avr/interrupt.h>
#ifndef F_CPU
#define F_CPU 16000000L
#endif

void init_timer_phase_correct_pwm(void);

int main(void)
{
    init_timer_phase_correct_pwm();
    while (1)
    {
    }
}

void init_timer_phase_correct_pwm(){

	DDRB |= (1 << PB4); //SET PIN COMPARE HARDWARE OC0B

	TCNT0 = 0;
	TCCR0A |= (1 << COM0B1) | (0 << COM0B0) | (0 << WGM01) | (1 << WGM00);
	TCCR0B |= (0 << WGM02) | (1 << CS02);
	OCR0B = 127;
}

 

That would seem to say that with TOP fixed the switching of the pin (OCR0B) takes place totally in hardware mode.

 

Below the waveform captured with my oscilloscope:

 

 

So, when you say that using OCR1A to fix the TOP I can't use A, do you mean that I can't use it purely in hardware mode, but if I use interrupts can I? If the interrupts are active, it is on the TOP event OCR1A change and imposed Compare Output mode COM1A1 = 1: COM1A0 = 0 (2) pin OC1A will be set to zero when TCNT1 up-counting, while OC1A will be set to 1 (HIGH level) as TCNT1 downcounting.
However, I wonder what could be the advantage or the use of generating a square wave with a variable duty cycle and variable frequency.

Which application can you find? From a theoretical point of view, have I understood well?  But in reality what advantage can there be in working this way?

Furthermore, I take advantage, but it is not clear to me when you say "therefore it is possible to use only the B channel (or OCR1B /) C1B) for the actual output". The premise was to set the TOP with OCR1A. But what do you mean and how do you do it?

I apologize for the very long post, for the inaccuracies and for my limited understanding of the subject, but I hope for your clarification. Any criticism, correction or advice will be really appreciated.
Thank you very much!

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codabat wrote:
I wonder what could be the advantage or the use of generating a square wave with a variable duty cycle and variable frequency.

 

A square wave can't have variable duty cycle, it's always 50% by definition, or else it's not a square wave. The general term is pulse wave. Yeah, pedantic, maybe, but you should use the correct terms to avoid confusion.

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El Tangas wrote:

A square wave can't have variable duty cycle, it's always 50% by definition, or else it's not a square wave. The general term is pulse wave. Yeah, pedantic, maybe, but you should use the correct terms to avoid confusion.

Hi El Tangas,
thank you. Your comment is not pedantic. Indeed it is extremely important, because having clarity on a definition, as you have said well, avoids confusion. This allows for better learning and improves the communication of one's thoughts in a more precise way. I really appreciated your observation. Thank you so much.

Have a nice day!

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codabat wrote:
The first thing that comes to mind is: what utility can this mechanism have?
Look again at:

 

 

So there are actually four different modes of operation: Normal, CTC, Fast PWM, Phase Correct PWM. Just concentrate on Fast PWM for now so you have modes 5, 6, 7, 14 and 15. Now note how they differ - presumably you have spotted it is in the "TOP" column? TOP says what is the highest number the timer will count to in this mode. In other words how many "ticks" in one cycle. In mode 5 the TOP value is 0xFF so the timer will count 256 steps from 0x00 to 0xFF. In mode 6 the TOP is 0x1FF so now it counts 512 steps from 0x000 to 0x1FF. For mode 7 it is 1024 steps from 0x000 to 0x3FFF. Before looking at 14 and 15 just consider the implication of that. Now I know the timer has CS bits that can set a prescaler that allows the period (/frequency) of the timer to be varied but let's say that did not exist and you could only select on/off where on was /1. Also consider that the CPU runs at a fixed frequency (forget CLKPR for now) so maybe it is a typical 8MHz ? This would mean:

 

For mode 5 (256 steps) PWM frequency = 8MHz / 256 = 31.25kHz

For mode 6 (512 steps) PWM frequency = 8MHz / 512 = 15.625kHz

For mode 7 (1024 steps) PWM frequency = 8MHz / 1024 = 7.8125kHz

 

and that is it. You don't get a choice about this - the counting range of the timer is fixed at 256/512/1024 steps depending on the mode you select and you can't change it. As I say, while the CPU speed remains at a fixed 8MHz the only possible change you can make is to vary CLKPR:

 

 

but all that lets you do is divide the 31.25/15.625/7.8125 by 2 or 4 or 8 or whatever. You still have a very limited range of frequencies available (and if you change CLKPR you change the entire speed of the whole AVR which you may not want either!). So now look at the last two (Fast PWM) modes in the table:

 

 

So now we have modes where TOP is no longer a fixed number. These two entries are saying that TOP can be varied by setting the ICR1 or OCR1A registers. Unless using input capture then the one where it is set by ICR1 is possibly the "better" of the two options. If you can vary the frequency with ICR1 then it leaves both OCR1A and OCR1B for setting the duty cycle ratio on channels A and B - so both are still usable. But say you were also using the input capture feature then you may want to be able to use ICR1 so then you are left with mode 15. That now uses OR1A to set TOP (frequency) so it can't be used for duty - so channel A is not available in this mode - but you still have OCR1B and therefore have to use that for the actual PWM.

 

The advantage of these modes is that (within reason) you can hit or get close to almost any frequency you require. Say you are running at 8MHz but you want the PWM signal to be close to 500Hz. So you pick mode 14/15 then set ICR1 or OCR1A to 15,999. Now the timer counts 16,000 steps from 0 to 15999 so the timer frequency is 8MHz / 16000 = 500Hz. If you wanted to I guess you could set TOP to 256 or 512 or 1024 and emulated modes 5, 6 or 7 but you might as well just pick those modes if that's what you require.

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Hi, dear Clawson,
I thank you for your explanations. I begin to understand better. Probably, maybe I'm wrong, the function and the possibilities of use of the channels are not yet obvious to me.

I still have difficulty understanding when you say:
  "That now uses OR1A to set TOP (frequency) I know it can't be used for duty - so channel I am not available in this mode - but you still have OCR1 and therefore have to use that for the actual PWM."

What do you want to tell me? Perhaps with OCR1A, I set the frequency of the timer and that with the channel "B" (OCR1B) I set the duty cycle and therefore it will be from the PD4  pin that I will have the PWM?

 

In other words, I could write:

 

void init_timer_phase_correct_pwm(){

	DDRD |= (1 << PD4); 

	TCNT1 = 0;
	TCCR1A |= (1 << COM1B1) | (0 << COM1B0) | (1 << WGM11) | (1 << WGM10);
	TCCR1B |= (1 << WGM13) | (0 << WGM12) | (1 << CS12);
	OCR1A = 624;
	OCR1B = 312;

}

(frequency 50Hz and duty cycle 50%).

 

Perhaps I need to go deeper into the concept of the channel. And the concept of double buffering on the OCRnA / B register.

 

Sorry again and I hope to be able to send you my most sincere thanks.

Thanks again!

Last Edited: Wed. Sep 18, 2019 - 07:30 PM
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codabat wrote:
(frequency 50Hz and duty cycle 50%).

Really?  More on that a bit later.  First, as mentioned earlier, most of us would not use a PWM mode for a 50% duty cycle.  (In fact, for me it muddies the discussion to try to demonstrate PWM by using 50% duty cycle.)  We'd use CTC.  And almost assuredly I wouldn't use a phase-correct mode for this simple task.

 

Surely, before we could agree on 50Hz we'd need to know the speed of your AVR, and the model to check the register settings.  If we scroll all the way to the top of the thread there is a mention of Mega164A.  Is that what we are asserting?  Put that info in the query post.  There is a 16MHz in a couple of the code snippets; implied because it is only the override value.  Is 16MHz what we are asserting?  Put that info in the query post.

 

codabat wrote:
What do you want to tell me?

That the different modes, types of timer operations, have different meaning for stuff to carry out the operation. 

 

If I read your code snippet correctly, you are calling for Mode 15, correct?  From the chart above, that is Fast PWM with OCR1A as TOP.  Yet the code snippet says

codabat wrote:

init_timer_phase_correct_pwm

   For us to agree, it would be nice if the situation was clear.

 

So, does it work?  You have been given a step-by-step to use Studio simulator.  What results did you get?  Or do you want us to take your code snippet and do that for you?

 

CodeVisionAVR Wizard indeed suggests PD4 for OC1B.  But it comes up with a 10ms period if the main clock is 16MHz.  [I'd think it would be an odd number for OCR1A myself; now I'm wondering what >>I<< am missing.]

// Timer/Counter 1 initialization
// Clock source: System Clock
// Clock value: 62.500 kHz
// Mode: Fast PWM top=OCR1A
// OC1A output: Disconnected
// OC1B output: Non-Inverted PWM
// Noise Canceler: Off
// Input Capture on Falling Edge
// Timer Period: 10 ms
// Output Pulse(s):
// OC1B Period: 10 ms Width: 5 ms
// Timer1 Overflow Interrupt: Off
// Input Capture Interrupt: Off
// Compare A Match Interrupt: Off
// Compare B Match Interrupt: Off
TCCR1A=(0<<COM1A1) | (0<<COM1A0) | (1<<COM1B1) | (0<<COM1B0) | (1<<WGM11) | (1<<WGM10);
TCCR1B=(0<<ICNC1) | (0<<ICES1) | (1<<WGM13) | (1<<WGM12) | (1<<CS12) | (0<<CS11) | (0<<CS10);
TCNT1H=0x00;
TCNT1L=0x00;
ICR1H=0x00;
ICR1L=0x00;
OCR1AH=0x02;
OCR1AL=0x70;
OCR1BH=0x01;
OCR1BL=0x38;

 

 

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Wed. Sep 18, 2019 - 09:28 PM
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codabat wrote:
What do you want to tell me?
I am trying to help you understanding. I cannot help wondering if you are over thinking this. The choice is really easy (for Fast PWM). if you want variable frequency you use mode 14 or 15. If you want both channels active while doing it you use mode 14. If you want to do both PWM and input capture and are willing to sacrifice channel A then you use mode 15.

 

This all comes back to your original requirements for your micro design. Do you need PWM at all? If so does it need to be phase correct or is "fast" OK? Do you need to be able to vary frequency? How many channels do you need active? 

 

When you have answered all those questions you should have narrowed you choice down to the correct one of the 15 available WGM modes.

 

Or is this just like a selection in a sweet shop? Why would I favour the mint imperials over the rhubarb and custards ?

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Hi theusch,
Excuse me. I am aware of having confused the discussion. First of all because as you rightly pointed out to me, I didn't give all the necessary information. Furthermore, I now realize that I have not correctly explained my doubts and my need for clarification.

I specify that the study I am doing using an ATMEGA164 in combination with a Crystal 16Mhz.

I agree, and I understand that you want a square wave (duty cycle 50%) it is convenient to use the CTC mode.
My intent was purely speculative, aimed at verifying the understanding of the concepts and possibilities offered by the various methods of using the timers/counters and how to generate generic waves.

What was not clear to me is the concept of the channel ("A" and "B").

No, the code I posted configured a Waveform Generation mode 11, ie, a PWM, Phase Correct with TOP set by OCRnA and with TOVn upon reaching the BOTTOM.

I apologize once again if I cannot express my thoughts correctly. What I did not understand - I start now, I believe, and I hope so - to understand something more about the concept of a channel. In fact, in the timers with TOP fixed the OCRnA register allows activating the impulses in a total hardware way. While correct if I am wrong in this mode by acting as the upper limit, the channel for the counter changes the physical behavior of the associated physical pin.
In fact, once the frequency of the timer has been set, by means of the 16Mhz crystal and the chosen Prescaler the OCRnA register (let's call it a channel) will govern only the period (and therefore the frequency) and if we want to generate a wave we need to resort to the " channel b "(OCRnB) to set the time ratio between 5V and 0V correctly.

Actually, I lingered onto play with PWM Phase Correct, using it even improperly and with a still low level of concepts, because this kind of mode is very interesting for me to understand. In fact, it seems to me ideal to be able to govern electric motors, in which it is crucial to be able to vary the speed of rotation (duty cycle) but keeping the frequency constant and the phase-controlled.

Consequently, to your observations, I have begun to experiment and to simulate what was said above. I try generating a simple fading of a led. With a trivial and raw implementation of the ISR (TIMER1_COMPB_vect).

 

void init_timer_phase_correct_pwm () {

DDRD | = (1 << PD4);
cli ();
TCNT1 = 0;
TCCR1A | = (1 << COM1B1) | (0 << COM1B0) | (1 << WGM11) | (1 << WGM10);
TCCR1B | = (1 << WGM13) | (0 << WGM12) | (1 << CS12);
OCR1A = 312;
OCR1B = 156;
TIMSK1 | = (1 << OCIE1B);
sei();
}

ISR (TIMER1_COMPB_vect) {
counter ++;
if (OCR1B> 0 && mode == 0) {
mode = 0;
OCR1B - = 2;
} else if (OCR1B <1 || OCR1B <312) {
mode = 1;
OCR1B + = 1;
if (OCR1B == 312) {
mode = 0;
counter = 0;
}
}
}

 

Here is the evidence of my oscilloscope:

 

As you can see, the time cycle varies with time, but phase and frequency are constant. For you, this will be obvious.

All this to tell you that I was and I am still - I answer you only now, because these days I have been busy with urgent things - trying to sharpen my understanding of how the two channels "A" and "B" influence the use of PIN and the ways and possibilities of generating waves.

But I stop here with the questions, you were all very kind to offer me your time and to share your comments with me. I continue to study, hoping to have begun to understand better certain concepts and nuances that I had not understood at first reading the documentation.

As you may have guessed, I didn't want anyone to try my code, but to try to better explain through them what seemed to me to be uncleared aspects.

Every criticism, consideration is always welcome and extremely important for me. But it is even more important to thank each of you for patiently dedicating your time and your knowledge contribution to help me.

Thanks a lot.

Last Edited: Mon. Sep 23, 2019 - 09:34 PM
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clawson wrote:

codabat wrote:
What do you want to tell me?
I am trying to help you understanding. I cannot help wondering if you are over thinking this. The choice is really easy (for Fast PWM). if you want variable frequency you use mode 14 or 15. If you want both channels active while doing it you use mode 14. If you want to do both PWM and input capture and are willing to sacrifice channel A then you use mode 15.

 

This all comes back to your original requirements for your micro design. Do you need PWM at all? If so does it need to be phase correct or is "fast" OK? Do you need to be able to vary frequency? How many channels do you need active? 

 

When you have answered all those questions you should have narrowed you choice down to the correct one of the 15 available WGM modes.

 

Or is this just like a selection in a sweet shop? Why would I favour the mint imperials over the rhubarb and custards ?

 

Dear Clawson,
I thank you for your extreme synthesis.
In a few words, I think you have made clear the way to set the problem and what are the questions that must be asked about the subject.

I apologize if I answer only now, but I've been busy with very urgent things. Only now can I return to these fascinating subjects and new knowledge.

When I opened the post, to tell the truth, the way is not very clear, I was trying to understand what the concept of channel means.

I wrote to theusch after his last speech. In the message I wrote it seems that I can say that the channels are not merely register, but intervene in the pin management mode, allowing the generation of waves in a "totally hardware mode"  as in the case of CTC mode, while in other cases change the way the wave is created (code support).

In summary, I was trying to understand a little better about the meaning of channel. So to do this, I tried empirically to understand what happened using, perhaps a little at random, the two registers (channels).

I think your considerations have already provided a way to reason and give an interpretation and the impact that the channels have.

Thank you again, if you feel you want to add further considerations and corrections to what I said, I am once again very grateful.

Thank you so much!