I've finished drawing the schematic for my weather data logger in Eagle and am starting my very first PCB layout. I have a few questions:
1. The board will be two layers. Should I put the ground plane on the front (component) side or the back of the board?
2. Should I use both a ground plane and a power plane (3.3v), or is a ground plane sufficient?
3. I have one 100nF ceramic chip cap per IC for bypass--is this enough, or do I need more?
Which side is ground is not important.
jim
But consistency in your own designs probably will help with later projects.
I tend to use a ground plane on the back and a vcc plane on the front, but that's not a guarantee if it's a busy board.
I do not think you mentioned which uC you are using.
You need one by-pass cap for each pair, (V+ & Gnd), of power pins on the uC, if it has more than one pair.
JC
Those are copper pour, not power/ground planes. The latter are used on multilayer boards.
Leon,
Yes, they are copper pours, but Eagle has the option of connecting nets, such as GND or +3.3v, to the pours.
Wether you call it a plane or a pour, the most important thing is that you give your circulating currents a short and direct path back to where they came from.
Dumping everything into a pour or a plane is better than randomly connecting the power and ground. It's not better than discrete return paths with the loop areas minimized.
I see this issue over and over again with boards at part 15 testing, where oscillators are radiating. You attach a shielded cable to the board, and it gets worse! This is symptomatic of high frequency current dumped into a ground plane or pour. Think of it as an infinite plane grid of inductors and/or resistors. The current will take ALL possible paths home. If you return the current on discrete tracks, then it can only take the prescribed path home.
On the bypass subject, the size of the bypass cap is determined by operating frequency. You need effective bypassing at Fclk and at several harmonics, up through at least the 9th harmonic of the oscillator. Get a data sheet for your caps and see where their impedance is lowest.
Are there any hobbyist-level sites or literature that explains the nuances of PCB layout? Most of what I've seen is directed at professionals designing boards with gigahertz signals and other critical layout issues. I'd like something directed at a hobbyist laying out a simple two-layer board with a 10 MHz AVR and relatively slow peripherals.
The information given by dbvanhorn is excellent and definitely required if you are going to mass produce something that must be certified. For your application, you probably don't need to worry about this. The 0.1uF cap near the power input of each IC that you are planning should be okay.
Smiley
Are there any hobbyist-level sites or literature that explains the nuances of PCB layout? Most of what I've seen is directed at professionals designing boards with gigahertz signals and other critical layout issues. I'd like something directed at a hobbyist laying out a simple two-layer board with a 10 MHz AVR and relatively slow peripherals.
It's not so much the frequency of the signal that is of concern, but the rise and fall times. If a signal has a rise/fall time which is faster than the time taken for a signal to propagate down the trace (about 66% speed of light) then it becomes a transmission line. Reflections caused by impedance mismatch are less likely to cause data corruption on low frequency signals, but can cause double clocking errors or similar effects.
-Tim
The main thing to watch with slow systems like those using an AVR are the ground and power connections.
I used top layer ground pours for Through Hole component designs (since I lay out as much tracks as possible on the solder side), and bottom layer pours for SMD designs (since I only connect to GND from time to time and this way all tracks remain on the top side). If you flood your board with connected ground pours and you use relatively safe sensors (I mean no Pt100 neither Thermocouples - been there, done that), then you don't need to worry too much about other issues, but some more information about your design could be helpful.
Fascinating to see so many design paradigms.
Just to be different, with through plate I use a ground pour on one side and a vcc pour on the other, and (depending on IC orientation, which depends on the circuit topology to a large extent) north-south routes on one side and east-west on the other.
That said, many of my recent designs have been a few dozen TTL chips to a board...
Are there any hobbyist-level sites or literature that explains the nuances of PCB layout? Most of what I've seen is directed at professionals designing boards with gigahertz signals and other critical layout issues. I'd like something directed at a hobbyist laying out a simple two-layer board with a 10 MHz AVR and relatively slow peripherals.
Just to be different, with through plate I use a ground pour on one side and a vcc pour on the other, and (depending on IC orientation, which depends on the circuit topology to a large extent) north-south routes on one side and east-west on the other.
Off-hand, it seems like this would tend to encourage large current loops, since the return paths are orthogonal to the supply paths (i.e., following the gaps between routes).
Michael
Quite probably, Michael - though I haven't had it be a problem yet. What I do tend to find is that the majority of the paths run in one direction, with relatively few on the other side. Maybe some unconscious bias?
Most important of all is the return path. Understand this first of all. Ground planes are very important mainly at RF signals.
I've finished drawing the schematic for my weather data logger in Eagle and am starting my very first PCB layout. I have a few questions:1. The board will be two layers. Should I put the ground plane on the front (component) side or the back of the board?
2. Should I use both a ground plane and a power plane (3.3v), or is a ground plane sufficient?
3. I have one 100nF ceramic chip cap per IC for bypass--is this enough, or do I need more?
1) Try to make the bottom layer a single ground plane with no components on it. It will become a solid ground reference, screen electrical fields and it is easier and cheaper (in production process) if all components are mounted from the same side.
2)The power traces to each IC doesn't need to be part of a big power plane unless the IC's draw a lot of current. The (long) power traces can act like LC filter together with the bypass capacitor at each IC.
3) Read the data sheet. Usually 100nF is sufficient close to each IC.
Barring any recommendations in the data sheet, I usually use one 100nF cap per power pin on the device.
/mike
