Paged Memory

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Hello, when i gone through a AVR compiler co-design pdf i encountered paged and unpaged direct addressing mode. I am pretty much clear about direct addressing mode but i am unable to comprehend the paged and unpaged. I did a little bit of googling but i can't get an exact picture of what the pdf is trying to say. Can anyone brief me about it.

Thanks in advance.

-Krishna Balan S

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"Heroes are ordinary people with extraordinary commitment"

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Before we clarify paged addressing modes, may i kindly ask what an

Quote:
AVR compiler co-design pdf
is???

Maybe you could even provide a link?

Einstein was right: "Two things are unlimited: the universe and the human stupidity. But i'm not quite sure about the former..."

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Which chip in particular are you referring to? Anything with 64K or less of flash doesn't have any paged memory.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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The link is here. www.atmel.com/atmel/acrobat/comp...

Yes, I am referring to chips having more than 64KBytes.

-Krishna Balan S

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"Heroes are ordinary people with extraordinary commitment"

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That's only talking about SRAM, there are no chips with 64K of ram unless you use external ram which is supported by only a few chips.

I have used AVR for about 10 years and NEVER even known about that document, I'm not sure exactly how it affect you in programming AVRs. Are you planning on using more than 64K of ram?

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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No !. My intention is to know what is meant by paged addressing mode and unpaged addressing mode. I may get a chance to use external SRAM near future.

-Krishna Balan S

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"Heroes are ordinary people with extraordinary commitment"

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Quote:

No !. My intention is to know what is meant by paged addressing mode and unpaged addressing mode. I may get a chance to use external SRAM near future.

The address bits for external RAM space only allow for a certain address range - the limit with 16 bit is of addressing will be 64K (though because of the SFRs and internal SRAM not all this may be accessible). If you wanted to add 256K of external SRAM to a mega162 or mega128 (say) then you'd use an additional two IO lines to provide A16 and A17 and would set these by direct IO access (PORT pins). The two wires would select one of four possible arrangements (00, 01, 10 and 11) and then the usual ext RAM addressing mechanism would provide A0..A15. So the 256K is effectively divided into four pages of 64K. THAT is paged addressing.

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Thank you Clawson.

-Krishna Balan S

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"Heroes are ordinary people with extraordinary commitment"

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A "page" is nothing more than a fancy way to define part of an address bus. In one of my AVR projects using external SRAM, I have a 512K SRAM connected. I like to think I have 8 pages of 64K memory.

So, I consider the first 16 bits of the address bus to be the main address bus and then use the leftover 3 bits to select 1 of 8 pages.

The benefit to this seemingly redundant naming system is that the page bits can be latched or controlled using some internal functionality while allowing an easy and fast access to the initial 8 or 16 bits of address space.

19 bit math is ugly on an 8 bit AVR, but 8 pages of 16 bits is not so bad!

Brad

I Like to Build Stuff : http://www.AtomicZombie.com