OUT vs STS

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Hi,

I'm currently trying to understand what is going on in the sp_driver.s file from Atmel. And I'm not failing completely, I think.

But there is one thing I don't understand. In some of the functions, the contents of RAMPZ are first "pushed" into r19, and later "popped" back. The instructions used are
in r19, 0x3b
...
out 0x3b, r19

This makes sense. But writing to CCP is done like this:
ldi r18, 0x9D
sts 0x0034, r18

As I see things, out 0x34, r18 would do exactly the same thing as sts 0x034, r18. Except that "out" would take one byte and one clock cycle less than "sts". So why did someone choose "sts"?

I know it's not a big deal, but if one of you has a logical explanation, I'd like to see it.

Erik

You're absolutely right. This member is stupid. Please help.

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Quote:

So why did someone choose "sts"?

Is this Asm or C? If C the compiler it should just naturally optimise an STS in the range 0x00 to 0x3F into an OUT which suggests an Asm macro might have been used.

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Quote:

Is this Asm or C? If C the compiler it should just naturally optimise an STS in the range 0x00 to 0x3F into an OUT which suggests an Asm macro might have been used.

Cliff--perhaps reference http://www.hs-augsburg.de/~schwa... and search for "CCP". with a quick pass, and verifying from one of the Xmega "family" manuals that CCP and RAMPZ are in the same "CPU" address block and less than STS-needed address, I understand OP's query.

Are there models, perhaps, where those addresses are >>not<< in the same CPU block?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Quote:
Is this Asm or C?

Sorry. It is Asm as macros in C (i think). And what I'm studying is the .lss file from the result.

The original (excerpt) looks like this:

SP_CommonSPM:
	movw	ZL, r24          ; Load R25:R24 into Z.
	sts	NVM_CMD, r20     ; Load prepared command into NVM Command register.
	ldi	r18, CCP_SPM_gc  ; Prepare Protect SPM signature in R18
	sts	CCP, r18         ; Enable SPM operation (this disables interrupts for 4 cycles).
	spm                      ; Self-program.
	clr	r1               ; Clear R1 for GCC _zero_reg_ to function properly.
	out	RAMPZ, r19       ; Restore RAMPZ register.
	ret

and from the .lss file:

000203d6 :
   203d6:	fc 01       	movw	r30, r24
   203d8:	40 93 ca 01 	sts	0x01CA, r20
   203dc:	2d e9       	ldi	r18, 0x9D	; 157
   203de:	20 93 34 00 	sts	0x0034, r18
   203e2:	e8 95       	spm
   203e4:	11 24       	eor	r1, r1
   203e6:	3b bf       	out	0x3b, r19	; 59
   203e8:	08 95       	ret

Here, "sts" and "out" are clearly visible. Elsewhere in the code, there is a corresponding "in".

But I believe you have a point, Theusch. sp_drivers.s is made for all xmega microcontrollers. There may be parts where CCP is located above 0x3F. Thus, sts may be necessary in some situations.

I think I'll just leave it at that. Thank you very much for your feedback.

Br, E

You're absolutely right. This member is stupid. Please help.

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Quote:

There may be parts where CCP is located above 0x3F.

It's not that:

iox128a1.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128a1u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128a3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128a3u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128a4u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128b1.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128b3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128c3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128d3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox128d4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox16a4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox16a4u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox16c4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox16d4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox16e5.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox192a3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox192a3u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox192c3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox192d3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox256a3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox256a3b.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox256a3bu.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox256a3u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox256c3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox256d3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox32a4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox32a4u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox32c4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox32d4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox32e5.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox384c3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox384d3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64a1.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64a1u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64a3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64a3u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64a4u.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64b1.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64b3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64c3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64d3.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox64d4.h:#define CPU_CCP  _SFR_MEM8(0x0034)
iox8e5.h:#define CPU_CCP  _SFR_MEM8(0x0034)

(this results is probably not a surprise as the entire Xmega range is supposed to be homogeneous with any common SFRs always at the same location).

If it is Asm macros I think the author simply made a mistake and didn't realise she could use OUT at this point. If just referring to CPU_CCP in the Asm source it may not have been immediately obvious that the register was in range of OUT.

(of course good Asm programmers use a macro like Atmel's own STORE() macro so they don't have to look these things up)

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Yeah, of course it could just be a simple error, which goes completely unnoticed, because the stuff obviously works.

STORE()? Hmmm... I didn't know that one. But then again, I don't claim to be a good Asm programmer. :wink:

You're absolutely right. This member is stupid. Please help.

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Quote:

STORE()? Hmmm... I didn't know that one.

Atmel App Note AVR001