NOR gate few questions

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xtal_88
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Posted by xtal_88: Wed. Dec 11, 2013 - 10:14 AM
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Hi !

I would like to connect 2 uC via NOR gate:

http://www.ti.com/lit/ds/symlink/cd74hc4002.pdf

This is start phase, so no USART, TWI or SPI at the moment.


I need to detect positive impulses on uC 1, duration of 1 second.

INTERRUPT on uC 2 is active low.

My plan looks like this (in picture).

Few questions came to my mind:

1. About pull-up resistor R1

a)Do I actually need R1 or 1Y does do it for me(I mean if there are no pulses 1Y is HIGH)?

b)Can I internally enable pull-up resistor on INT 1 of uC 2?

c)Can I leave R1 as is in picture?

2. What should I do with other inputs on NOR gate and Y2 which aren't used?

a)2A 2B 2C 2D tie to GND and Y2 leave floating

b)2A 2B 2C 2D tie to Vdd and Y2 leave floating

Thing here is to minimize power consumption.

3. What do I need to do to minimize possible electro-magnetic interference on:

a) uC 1 <-> NOR gate side

b) NOR gate <-> uC 2 side

Other solution are welcome too!

Thank you, guys !

Attachment(s): 

Image icon nor_gate.JPG

Tags:

Learning and Information, General Electronics
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Kartman
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Posted by Kartman: Wed. Dec 11, 2013 - 11:18 AM
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1. R1not required. The nor gate will actively drive high or low. No pullup required internal or external.

2. Tie the inputs high or low. The output can be left open.

3. The impedances are fairly low, so nothing pecific required. If there are long wires involved, this may cause problems.

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xtal_88
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Posted by xtal_88: Wed. Dec 11, 2013 - 11:53 AM
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Kartman wrote:

3. The impedances are fairly low, so nothing pecific required. If there are long wires involved, this may cause problems.

Thank you for answers !

2 boards are involved:

1st board: uC 1

2nd board: NOR + uC 2

connection between them is 10 wire flat cable, 5 Inch max

Both boards are in plastic housing and they are near energy cables (10 or 20 kV).

Could this cause a problem ?

Uuuups..

Forgot to say that I need to decode input signals.

So schematics would look like this

Attachment(s): 

Image icon nor_gate.JPG
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bloody-orc
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Posted by bloody-orc: Wed. Dec 11, 2013 - 12:52 PM
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so why is the INT and the NOR gate even evolved? Just use Pin Change Interrupt on the uC2 and be done with it :)

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xtal_88
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Posted by xtal_88: Wed. Dec 11, 2013 - 01:34 PM
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bloody-orc wrote:
so why is the INT and the NOR gate even evolved? Just use Pin Change Interrupt on the uC2 and be done with it :)

OK, good point !

My uC is ATmega1281 and needs to be awaken on this PCINT.

Sleep mode is power save.

Quick look at datasheet, says PCINT can wake up uC.

Now is good time to try this.

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barnacle
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Posted by barnacle: Thu. Dec 12, 2013 - 06:30 AM
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In general, on circuits of this kind, you need to be aware not just of steady state conditions but also of the conditions which exist when one or the other processors is either powered off, is resetting, or has just plain crashed.

Most processors maintain configurable i/o pins as outputs *after* reset but it can be hard to find their configuration *during* reset, when the reset line is held low. Equally, if the two processors have setup routines that take differing times, you can find yourself in the situation where you have two output pins trying to drive each other.

The way to avoid damage there is to limit the maximum current that can flow between the ports with a series resistor. You need to maintain it both for the pin limit and the package limit but generally restricting it to a milliamp or two is safe - a couple of hundred ohms is a good start.

The final point is that if you're using a CMOS logic gate, its inputs are *very* sensitive to static charge and when the driving processor is not yet configured or is unpowered, you may need to pull its inputs (220k or so) up or down as required.

(captcha)

Neil Barnes
www.nailed-barnacle.co.uk

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xtal_88
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Posted by xtal_88: Thu. Dec 12, 2013 - 10:15 AM
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Thank you barnacle for such detail answer !

I need to detect positive impulses duration of 1 sec.

Idea is uC 2 sleeps most of the time and is awaken by uC 1 through it's pins P1-4.
When positive pulse comes NOR gate wakes up uC 2(that's why 1Y is on INT).

When uC 2 is awaken it waits for 200-300 ms and reads pin states of uC 1 to decode what actually caused interrupt.

New sch is here. Is this how it should look like according to your suggestions?

This also applies to other 3 ports, P1-2 of uC 1.

I added capacitor in parallel to 100k. Is this OK? It's value is 33pF.

Maybe this could be done with optocouplers or some other way, but thing is that power consumption has to be very low since both uC are battery powered.

So any other ideas ?

Thank you !

Attachment(s): 

Image icon nor_gate.JPG
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Chuck-Rowst
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Posted by Chuck-Rowst: Thu. Dec 12, 2013 - 08:02 PM
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Quote:
Both boards are in plastic housing and they are near energy cables (10 or 20 kV).

How near? AC or DC? What freq? What current is flowing thru them and how does it vary with time?

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xtal_88
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Posted by xtal_88: Thu. Dec 12, 2013 - 08:31 PM
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Chuck-Rowst wrote:
Quote:
Both boards are in plastic housing and they are near energy cables (10 or 20 kV).

How near? AC or DC? What freq? What current is flowing thru them and how does it vary with time?

3-4 meters
AC 50Hz
10 kV
100-150 A

[Re:]how does it vary with time?
Depends on power load in electric grid

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Chuck-Rowst
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Posted by Chuck-Rowst: Fri. Dec 13, 2013 - 02:51 PM
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xtal_88,

It's fair to say you can anticipate electrical interference problems from the "energy cables".

Are these "energy cables" in a situation which will allow testing of your prototype(s) in their final installation position(s)?

Are these aerial cables? Are they enclosed in conduit? Are the cables buried? Are they single phase or 3-phase? How far apart are the conductors? Where is your box situated with respect to all of the "high energy" cables?

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barnacle
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Posted by barnacle: Sat. Dec 14, 2013 - 05:28 PM
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xtal_88 wrote:

So any other ideas ?

You don't need the pull-up resistor on the interrupt line unless the or gate is going to be unpowered at any time; you will need a series resistor between the or gate and the interrupt if the interrupt line is a normal i/o which could bw in an indeterminate state during reset.

You need pullups (suggest 220k) on the inputs to the or gate.

You need series resistors (suggest 220 ohm but check your current limits on the chips) between the outputs of the left processor and the inputs of the right processor.

Neil Barnes
www.nailed-barnacle.co.uk

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