Non Maskable Interrupt

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Hi freaks, just a quick question.  The NMI Interrupt is handled in the exception.s file.  Can you disable the NMI by Disabling exceptions? 

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Last Edited: Wed. Jul 18, 2018 - 06:36 PM
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Fianawarrior wrote:
Can you disable the NMI by Disabling exceptions?
I don't know UC3 (few people do) but in my experience the NM in NMI means "Non Maskable". The point being that this is an interrupt that is bound to occur.

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clawson wrote:
in my experience the NM in NMI means "Non Maskable"

Likewise.

 

 

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If you set a interrupt to the level "non maskable" then it is what the text says ;)  non maskable. Guess you have to disable all interrupts at the highest level, or set the interrupt level to a maskable lavel.

 

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A check of the datasheet shows that NMI is a pin that generates an interrupt that cannot be masked. Presumably this is to be connected to some external device in the circuit that MUST be serviced above all else. Presumably the way to prevent getting them is simply to wire the pin to a non-active state?

 

EDIT: Actually, reading on (just Ctrl-F for "NMI") I come to:

 

I wonder if the question here is about NMI at all or is it about disabling things like non-aligned fetch exceptions etc?

Last Edited: Fri. Jul 13, 2018 - 11:50 AM
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A Claytons NMI - 'the NMI you have, when you're not having an NMI'. It sounds like it is more of a high priority interrupt than non-maskable.

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I think what Cliff posted shows that the interrupt is non-maskable, but you can disable the input.

 

But, at the end of the day, it ends up with the same effect...

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From Exceptions and Interrupt Requests ;

Quote:
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits
acceptance of other events of the same or lower priority, except for the critical events
listed above.

(An "event" is an exception or an interrupt.)

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This is what I got back from microchip technical support:

 

The NMI will not be masked by the GM bit in Status Register. So, Global Interrupt Enable/Disable has no effect on this.
If the Exception Mask is set, it will result in a non-recoverable exception, requiring a system restart.
Manually disabling the EM bit is not recommended (acceptable only for debug purposes) and is automatically handled by the hardware.

So I guess not then.  

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Fianawarrior wrote:
So I guess not then.  

Did you not see #5 ?

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