multiple external interrupts

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i am using two interrupts sources and i have connected them to the int0 and int1 (any logical change should trigger int).

Almost every time (not every time), there is a chance of these interupts being triggered at the same time

so could i avoid the second interrupt by clearing the flag of the second interrupt in the last statement of isr of the first interrupt?

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Yes, that will clear the pending interrupt. I assume your ISR prologue turned off interrupts during the processing of your caught interrupt. You might want to look at the assembly output of your ISR and verify the first instruction is a CLI. It's possible if there interrupts come during the same CPU cycle that a second ISR can be called during the prologue of the caught interrupt if interrupts are not turned off quickly enough. As you likely know, most interrupt flags are cleared by writing a 1 to the flag bit.

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you mean only clearing flag might not do the required.

should i do a cli() at the beginning and at the end clear the flag and do sei() before coming out from the ISR?

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oops i forgot!!. the isr func in c would clear the interrupt before executing the instructions given in it.

so i think clearing the flag must do.
thank you bro

Last Edited: Sat. Feb 9, 2008 - 05:08 AM
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I'm sorry, I was mistaken. The interrupts will be automatically disabled when entering the ISR. The RETI at the end of the ISR will reset the interrupt flag to what its state was prior to entering the ISR. You shouldn't need to do any cli/sei in your ISR. Sorry for the confusion.

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no worry.
thank you .
thanks a lot

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hello bro i think our trick would not do.

coz the level interrupts donot use flags!

i only learnt this after failing practically wen i coded my robot for traversing chess board. :cry:

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ISR(PCINT0_vect)
{
  ...
  // Code to handle the event.
}

ISR(PCINT1_vect, ISR_ALIASOF(PCINT0_vect));

will the above code execute the ISR only once if both the interrupts occur simultaneously or if one occurs while the other is executing the ISR?

and what does the pin change interrupt0 vector mean?

how is it different from INT0?

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some reading of the datasheet is in order methinks!
If the interrupt is configured for level, it is only valid for the time it is at the active level, if configured for edge, when the edge occurs, the flag is set until the interrupt is serviced or the flag reset by code.
Think of the interrupt flags as being students in class putting their hands up - the teacher (AVR) can only talk to one student at a time. As mentioned by others, once in an ISR, further interrupts are disabled unless you specifically re-enable them. However, if other interupt sources become active, the respective flags are set so they will be processed once the current ISR has completed. If the interrupt is level, it must be active to be recognised when the AVR gets around to servicing its request.