Multiple Clock outputs to a Port Pin

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#1
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Hey,
I need to output my internal clock on two output PORT pins at the same time. I can get one output at the Pin7 of one of the PORTS easily by setting the CLKEVOUT register but I cant figure out how to obtain multiple outputs.
Do share if someone has some idea on this.

PS: I am running at 60 MHz using a PLL (if at all that helps)

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How on earth can an Xmega run at 60MHz - they are only specified for 32MHz operation.

Anyway, it's generally impossible to get F_CPU on a pin of an AVR apart from that single pin (CKOUT on older AVRs) that connects direct to the CPU clock. For any other pin you can only set timers to toggle them at F_CPU/2 or less. Similarly you can sometimes use SCK from the SPI but it's fastest speed is F_CPU/2 too.

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Quote:

How on earth can an Xmega run at 60MHz - they are only specified for 32MHz operation.

Using a PLL you can run a Xmega till 200 MHz. But somehow I am able to achieve clock till 60MHz only by using a 2 MHz clock with a 30x multiplication factor. I have checked 60MHz and its working.

Back to original problem, is there a way to just simply copy the values of a port to another port. I tried equating the PORTS but that doesnt work.

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Quote:

Using a PLL you can run a Xmega till 200 MHz. But somehow I am able to achieve clock till 60MHz only by using a 2 MHz clock with a 30x multiplication factor. I have checked 60MHz and its working.

Sure you can use multiplier values to get beyond 32MHz but as soon as you do you are running the chip beyond it's guaranteed performance limit. For a home hobby project this doesn't matter (who hasn't tweaked the multipliers on their old desktop PC to get better game frame rates? ;-)) but you cannot do this for a production application as half your devices are likely to fail in the field.

Nope, I personally cannot see a mechanism by which you can get it on more than one pin but surely some simple external logic would let you split it - or even just run the one line to two devices that need to be clocked?

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I believe it will perform fairly well till 60 MHz but at 72 MHz, it gets a little disturbed.

And I could split one clock to two points but I need the other clock to be the compliment of the first. I was thinking about using TGL to the other pin if only i could get it out at some other port pin.

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Quote:

I believe it will perform fairly well till 60 MHz

You are wrong - the only guarantee is that it will run well to 32MHz - after that all bets are off.
Quote:

but I need the other clock to be the compliment of the first.

Is this the reason God invented inverters?

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Quote:

You are wrong - the only guarantee is that it will run well to 32MHz - after that all bets are off.

The datasheet doesnt say anything for the frequency to be less than 32 MHz. But it does say that the output frequency of the PLL should lie between 10-200MHz. I am using a 32 MHz internal clock (which is guaranteed to be accurate) and then I am using a PLL within specified range. It is fair enough to expect accuracy which I am actually getting.

Quote:

Is this the reason God invented inverters?

Normal inverters does not work at such frequencies. I wanted to avoid buying high-frequency inverters.

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probloke wrote:
The datasheet doesnt say anything for the frequency to be less than 32 MHz.

Sure it does... witness:

Quote:
But it does say that the output frequency of the PLL should lie between 10-200MHz.

Where exactly does it say THAT???

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I am operating in the safe region of the CPU, i.e. 32 MHz. I am not overclocking the CPU. I am feeding that clock to the PLL whose safe range is till 200 MHz.
Go to page 90 of XMEGA A manual in the PLL section or refer to the attachment.

Attachment(s): 

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Quote:

I am running at 60 MHz

Sorry but what was the meaning of this text in the OP then? I took that to mean that the CPU was making opcode fetches at 60MHz.

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Hi probloke,
PLL maximum output frequency is different from CPU maximum applicable clock. I have tested XMEGA clock up to 64MHz but as Cliff said, this is not a safe area for working. There is a clkPER4 for applying to HIRES which can be up to 128MHz (or higher in overclock condition) and the PLL high frequency output range is for generation of clkPER4.

Ozhan KD
Knowledge is POWER

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@clawson - sorry for that confusion in my sentence.

@ Ozhan - Yes, I see what you are talking about HiRes there.

Thanks for the discussion here everyone.

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Probloke,

I think you are stuck. You can route the Clock to Port C, D, or E Pin 7. The setup registers do not allow you to feed it to multiple pins simultaneously.

I guess the thinking is that if you have the signal available on one pin, why would you need the same signal on a second pin?

There is no inverter option, so you are stuck using an external inverter if you need both signals, (Clk & Clk\).

You might have a close look at Peripheral 2x/4x clocks, to see if they would be useful in your application. I am not familar with them.

JC