Hello Everyone. I've been a long time absent due to illness and even now have to use 2 monitors to be able to use my Personal Confusor.
Anyway... With assistanve I have contined to design electronic products and am currently working on a dual ATMEGA2560 MP design. I had an udea about optimizing performance: using dual port RAN in eternal memory space of both processors to allow highet speed inter-procssor communications.
Of course the big lmitartion is tht these processors do not have an external bus cycle wait state mechanism. Hence I may have to resott to co-operative resource-sharing of thid mrmory, which is a shame becwuse ots less than ideal performance.
Another idea is to use clock-strtching to add wait states into rcternal bus acssses. Hoever that probablu only would work if the procssor is fully-static in operation.
I have yet to find any information on bus cycle manipulation using the external clock, so this idea remains theoretical.
Can anyone shad some light?